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[174.21.150.71]) by smtp.gmail.com with ESMTPSA id t5sm10938200pjr.22.2020.12.31.08.43.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Dec 2020 08:43:17 -0800 (PST) Subject: Re: [PATCH 1/3] target/arm: keep translation start level unsigned To: =?UTF-8?Q?R=c3=a9mi_Denis-Courmont?= , qemu-arm@nongnu.org References: <7884934.NyiUUSuA9g@basile.remlab.net> <002743e6-10d3-88b3-961a-8571efb4d1ed@linaro.org> <9468010.vzF1F9XyNR@philogene> From: Richard Henderson Message-ID: <1b14279c-f620-5c03-b25c-a52fa370cc8e@linaro.org> Date: Thu, 31 Dec 2020 08:43:15 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <9468010.vzF1F9XyNR@philogene> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -54 X-Spam_score: -5.5 X-Spam_bar: ----- X-Spam_report: (-5.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.399, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, remi.denis.courmont@huawei.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/31/20 1:59 AM, Rémi Denis-Courmont wrote: > Le jeudi 31 décembre 2020, 00:38:14 EET Richard Henderson a écrit : >> On 12/30/20 2:10 PM, Richard Henderson wrote: >>> On 12/18/20 6:33 AM, remi.denis.courmont@huawei.com wrote: >>>> From: Rémi Denis-Courmont >>>> >>>> Signed-off-by: Rémi Denis-Courmont >>>> --- >>>> >>>> target/arm/helper.c | 14 ++++++-------- >>>> 1 file changed, 6 insertions(+), 8 deletions(-) >>> >>> The patch does more than what is described above. >>> >>>> diff --git a/target/arm/helper.c b/target/arm/helper.c >>>> index df195c314c..b927e53ab0 100644 >>>> --- a/target/arm/helper.c >>>> +++ b/target/arm/helper.c >>>> >>>> @@ -10821,17 +10821,12 @@ do_fault: >>>> * Returns true if the suggested S2 translation parameters are OK and >>>> * false otherwise. >>>> */ >>>> >>>> -static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level, >>>> +static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint32_t >>>> level, >>>> >>>> int inputsize, int stride) >>>> >>>> { >>>> >>>> const int grainsize = stride + 3; >>>> int startsizecheck; >>>> >>>> - /* Negative levels are never allowed. */ >>>> - if (level < 0) { >>>> - return false; >>>> - } >>>> - >>> >>> I would expect this to be the only hunk from the patch description. >>> Probably changing this negative check to a >= 3 check. >> >> Having read the next patch, I think you should drop this type change. >> >>>> @@ -11203,7 +11201,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, >>>> uint64_t address,>> >>>> if (!aarch64 || stride == 9) { >>>> >>>> /* AArch32 or 4KB pages */ >>>> >>>> - startlevel = 2 - sl0; >>>> + startlevel = (2 - sl0) & 3; >> >> This hunk belongs with the next patch, implementing TTST, and should be >> conditional. I.e. >> >> if (stride == 9) { >> startlevel = 2 - sl0; >> if (aarch64 && >> cpu_isar_feature(aa64_st, env_archcpu(env)) { >> startlevel &= 3; >> } > > You can do that but: > 1) Nothing in the spec says that SL0 == b11 without ST means start level -1. > It's undefined, and I don't see any reasons to treat it differently than with > ST. By that logic there's no reason to treat it differently at all; you could drop the feature check entirely. In lieu, -1 makes a decent error indicator. > 2) Functionally, checking for ST seems to belong naturally within > check_s2_mmu_setup() in this particular case. I guess. I'll leave it to Peter's preference. r~