From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com
Subject: [PATCH v2 06/27] target/riscv: Add the Hypervisor CSRs to CPUState
Date: Fri, 25 Oct 2019 16:23:28 -0700 [thread overview]
Message-ID: <1b9ba32053453869847f39afb38b5c5cc53ccb8b.1572045716.git.alistair.francis@wdc.com> (raw)
In-Reply-To: <cover.1572045716.git.alistair.francis@wdc.com>
As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip
is 32-bit as well.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
---
target/riscv/cpu.h | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bb7a0e27a7..a1625e8af0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -145,6 +145,23 @@ struct CPURISCVState {
target_ulong mcause;
target_ulong mtval; /* since: priv-1.10.0 */
+ /* Hypervisor CSRs */
+ target_ulong hstatus;
+ target_ulong hedeleg;
+ target_ulong hideleg;
+ target_ulong hgatp;
+
+ /* Virtual CSRs */
+ target_ulong vsstatus;
+ uint32_t vsip;
+ target_ulong vsie;
+ target_ulong vstvec;
+ target_ulong vsscratch;
+ target_ulong vsepc;
+ target_ulong vscause;
+ target_ulong vstval;
+ target_ulong vsatp;
+
target_ulong scounteren;
target_ulong mcounteren;
--
2.23.0
next prev parent reply other threads:[~2019-10-25 23:32 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-25 23:23 [PATCH v2 00/27] Add RISC-V Hypervisor Extension v0.4 Alistair Francis
2019-10-25 23:23 ` [PATCH v2 01/27] target/riscv: Don't set write permissions on dirty PTEs Alistair Francis
2019-10-25 23:23 ` [PATCH v2 02/27] target/riscv: Add the Hypervisor extension Alistair Francis
2019-10-25 23:23 ` [PATCH v2 03/27] target/riscv: Add the virtulisation mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 04/27] target/riscv: Add the force HS exception mode Alistair Francis
2019-10-25 23:23 ` [PATCH v2 05/27] target/riscv: Fix CSR perm checking for HS mode Alistair Francis
2019-10-25 23:23 ` Alistair Francis [this message]
2019-10-25 23:23 ` [PATCH v2 07/27] target/riscv: Print priv and virt in disas log Alistair Francis
2019-10-25 23:23 ` [PATCH v2 08/27] target/riscv: Dump Hypervisor registers if enabled Alistair Francis
2019-10-25 23:23 ` [PATCH v2 09/27] target/riscv: Add Hypervisor CSR access functions Alistair Francis
2019-10-25 23:23 ` [PATCH v2 10/27] target/riscv: Add Hypervisor virtual CSRs accesses Alistair Francis
2019-10-25 23:23 ` [PATCH v2 11/27] target/riscv: Convert mie and mstatus to pointers Alistair Francis
2019-10-25 23:23 ` [PATCH v2 12/27] target/riscv: Add virtual register swapping function Alistair Francis
2019-10-25 23:23 ` [PATCH v2 13/27] target/riscv: Add support for virtual interrupt setting Alistair Francis
2019-10-25 23:23 ` [PATCH v2 14/27] target/ricsv: Flush the TLB on virtulisation mode changes Alistair Francis
2019-10-25 23:24 ` [PATCH v2 15/27] target/riscv: Generate illegal instruction on WFI when V=1 Alistair Francis
2019-10-25 23:24 ` [PATCH v2 16/27] riscv: plic: Always set sip.SEIP bit for HS Alistair Francis
2019-10-25 23:24 ` [PATCH v2 17/27] target/riscv: Add hypvervisor trap support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 18/27] target/riscv: Add Hypervisor trap return support Alistair Francis
2019-10-25 23:24 ` [PATCH v2 19/27] target/riscv: Add hfence instructions Alistair Francis
2019-10-25 23:24 ` [PATCH v2 20/27] target/riscv: Disable guest FP support based on virtual status Alistair Francis
2019-10-25 23:24 ` [PATCH v2 21/27] target/riscv: Mark both sstatus and vsstatus as dirty Alistair Francis
2019-10-25 23:24 ` [PATCH v2 22/27] target/riscv: Respect MPRV and SPRV for floating point ops Alistair Francis
2019-10-25 23:24 ` [PATCH v2 23/27] target/riscv: Allow specifying MMU stage Alistair Francis
2019-10-25 23:24 ` [PATCH v2 24/27] target/riscv: Implement second stage MMU Alistair Francis
2019-10-25 23:24 ` [PATCH v2 25/27] target/riscv: Add support for the 32-bit MSTATUSH CSR Alistair Francis
2019-10-25 23:24 ` [PATCH v2 26/27] target/riscv: Add the MSTATUS_MPV_ISSET helper macro Alistair Francis
2019-10-25 23:24 ` [PATCH v2 27/27] target/riscv: Allow enabling the Hypervisor extension Alistair Francis
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