From: Richard Henderson <richard.henderson@linaro.org>
To: Christoph Muellner <christoph.muellner@vrull.eu>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Jeff Law <jeffreyalaw@gmail.com>,
Tsukasa OI <research_trasio@irq.a4lg.com>,
liweiwei@iscas.ac.cn,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Rob Bradford <rbradford@rivosinc.com>
Subject: Re: [PATCH v5] riscv: Add support for the Zfa extension
Date: Fri, 30 Jun 2023 15:50:41 +0200 [thread overview]
Message-ID: <1c1a1c63-ed99-807c-7f21-b41a8a61b69c@linaro.org> (raw)
In-Reply-To: <20230630115239.1920012-1-christoph.muellner@vrull.eu>
On 6/30/23 13:52, Christoph Muellner wrote:
> +bool trans_fmvp_d_x(DisasContext *ctx, arg_fmvp_d_x *a)
> +{
> + REQUIRE_FPU;
> + REQUIRE_ZFA(ctx);
> + REQUIRE_EXT(ctx, RVD);
> + REQUIRE_32BIT(ctx);
> +
> + TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
> + TCGv src2 = get_gpr(ctx, a->rs2, EXT_ZERO);
> + TCGv_i64 t1 = tcg_temp_new_i64();
> + TCGv_i64 t2 = tcg_temp_new_i64();
> +
> + tcg_gen_ext_tl_i64(t1, src1);
> + tcg_gen_ext_tl_i64(t2, src2);
> + tcg_gen_shli_i64(t2, t2, 32);
> + tcg_gen_or_i64(t2, t2, t1);
> + tcg_gen_mov_i64(cpu_fpr[a->rd], t2);
This isn't right, because tcg_gen_ext_tl_i64 does signed extension.
But this whole operation is
tcg_gen_concat_tl_i64(cpu_fpr[a->rd], src1, src2);
(which isn't a great name, but chosen long ago).
You can also use EXT_NONE, since we'll be discarding the upper bits.
r~
next prev parent reply other threads:[~2023-06-30 13:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-30 11:52 [PATCH v5] riscv: Add support for the Zfa extension Christoph Muellner
2023-06-30 13:50 ` Richard Henderson [this message]
2023-06-30 14:03 ` Richard Henderson
2023-06-30 15:11 ` Christoph Müllner
2023-06-30 17:47 ` Richard Henderson
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