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From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
	Marc Zyngier <maz@kernel.org>
Subject: Re: [PATCH v6 14/14] target/arm: Use the max page size in a 2-stage ptw
Date: Mon, 5 Dec 2022 13:06:05 -0600	[thread overview]
Message-ID: <1c340eab-1a27-aec9-c9c0-62346550415c@linaro.org> (raw)
In-Reply-To: <CAFEAcA_5P+HgDjNJE6XZ7hN0TcOPOJfxzMANN9HQ8+b7R+34bw@mail.gmail.com>

On 12/5/22 10:50, Peter Maydell wrote:
>> @@ -2639,6 +2640,14 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
>>           return ret;
>>       }
>>
>> +    /*
>> +     * Use the maximum of the S1 & S2 page size, so that invalidation
>> +     * of pages > TARGET_PAGE_SIZE works correctly.
>> +     */
>> +    if (result->f.lg_page_size < s1_lgpgsz) {
>> +        result->f.lg_page_size = s1_lgpgsz;
>> +    }
>> +
>>       /* Combine the S1 and S2 cache attributes. */
>>       hcr = arm_hcr_el2_eff_secstate(env, is_secure);
>>       if (hcr & HCR_DC) {
> 
> Firstly, what if the lg_page_size is < TARGET_PAGE_SIZE ?
> I think this can't happen for VMSA, but for PMSA it will
> when the region (in either S1 or S2) is less than the page size
> (in which case lg_page_size is 0). Presumably in this case we
> want to set the result's lg_page_size to also be 0 to
> preserve the "don't put this in the TLB" effect.

Hmm, I hadn't considered that -- probably because I assumed a-profile.  You're right that 
we should preserve the "don't cache the result" behaviour.


> Secondly, how does this work for VMSA? Suppose that stage 1
> is using 4K pages and stage 2 is using 64K pages. We will then
> claim here that the result lg_page_size is 64K, but the
> attributes and mapping in the result are only valid for
> the 4K page that we looked up in stage 1 -- the surrounding
> 4K pages could have entirely different permissions/mapping.

This only works because the middle-end only registers one page, at TARGET_PAGE_SIZE.

But we need to record this as a large page, so that a flush of the (64k) stage2 page 
address affects all of the (4k) stage1 page entries that it covers.

Perhaps it would be less confusing in N target/ implementations if we have two 
lg_page_size structure members, and handle the unioning in the middle-end?  Soliciting 
suggestions for what to name such a beast (considering RME adds a stage3 lookup, and 
associated page/granule sizes), and how to signal that it is or isn't used (presumably 0, 
meaning that stageN+1 can't have a "don't record" setting).


r~



  reply	other threads:[~2022-12-05 19:07 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-24  5:18 [PATCH v6 00/14] target/arm: Implement FEAT_HAFDBS Richard Henderson
2022-10-24  5:18 ` [PATCH v6 01/14] target/arm: Introduce regime_is_stage2 Richard Henderson
2022-10-24  5:18 ` [PATCH v6 02/14] target/arm: Add ptw_idx to S1Translate Richard Henderson
2022-10-24 14:09   ` Alex Bennée
2022-10-24  5:18 ` [PATCH v6 03/14] target/arm: Add isar predicates for FEAT_HAFDBS Richard Henderson
2022-10-24  5:18 ` [PATCH v6 04/14] target/arm: Extract HA and HD in aa64_va_parameters Richard Henderson
2022-10-24 14:19   ` Alex Bennée
2022-10-24  5:18 ` [PATCH v6 05/14] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw Richard Henderson
2022-10-24  5:18 ` [PATCH v6 06/14] target/arm: Add ARMFault_UnsuppAtomicUpdate Richard Henderson
2022-10-24 14:53   ` Alex Bennée
2022-10-24  5:18 ` [PATCH v6 07/14] target/arm: Remove loop from get_phys_addr_lpae Richard Henderson
2022-10-24  5:18 ` [PATCH v6 08/14] target/arm: Fix fault reporting in get_phys_addr_lpae Richard Henderson
2022-10-24 14:55   ` Alex Bennée
2022-10-24  5:18 ` [PATCH v6 09/14] target/arm: Don't shift attrs " Richard Henderson
2022-10-24 11:52   ` Philippe Mathieu-Daudé
2022-10-24  5:18 ` [PATCH v6 10/14] target/arm: Consider GP an attribute " Richard Henderson
2022-10-24 15:06   ` Alex Bennée
2022-10-24  5:18 ` [PATCH v6 11/14] target/arm: Tidy merging of attributes from descriptor and table Richard Henderson
2022-10-24 15:20   ` Alex Bennée
2022-10-24  5:18 ` [PATCH v6 12/14] target/arm: Implement FEAT_HAFDBS, access flag portion Richard Henderson
2022-10-24  5:18 ` [PATCH v6 13/14] target/arm: Implement FEAT_HAFDBS, dirty bit portion Richard Henderson
2022-10-24  5:18 ` [PATCH v6 14/14] target/arm: Use the max page size in a 2-stage ptw Richard Henderson
2022-12-05 16:50   ` Peter Maydell
2022-12-05 19:06     ` Richard Henderson [this message]
2022-10-25 15:16 ` [PATCH v6 00/14] target/arm: Implement FEAT_HAFDBS Peter Maydell

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