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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from SN7PR11MB7540.namprd11.prod.outlook.com (2603:10b6:806:340::7) by PH0PR11MB5950.namprd11.prod.outlook.com (2603:10b6:510:14f::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7719.32; Thu, 4 Jul 2024 08:10:21 +0000 Received: from SN7PR11MB7540.namprd11.prod.outlook.com ([fe80::399f:ff7c:adb2:8d29]) by SN7PR11MB7540.namprd11.prod.outlook.com ([fe80::399f:ff7c:adb2:8d29%3]) with mapi id 15.20.7741.027; Thu, 4 Jul 2024 08:10:21 +0000 Message-ID: <1c480d3c-f501-43d4-a5ee-ce6cca171dab@intel.com> Date: Thu, 4 Jul 2024 16:14:16 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH ats_vtd v5 00/22] ATS support for VT-d To: CLEMENT MATHIEU--DRIF , "qemu-devel@nongnu.org" CC: "jasowang@redhat.com" , "zhenzhong.duan@intel.com" , "kevin.tian@intel.com" , "joao.m.martins@oracle.com" , "peterx@redhat.com" , "mst@redhat.com" , Clement Mathieu--Drif References: <20240702055221.1337035-1-clement.mathieu--drif@eviden.com> <1d0c56fe-b821-43c3-9e40-b686573ca840@intel.com> Content-Language: en-US From: Yi Liu In-Reply-To: Content-Type: text/plain; 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envelope-from=yi.l.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2024/7/4 12:36, CLEMENT MATHIEU--DRIF wrote: > > On 03/07/2024 14:32, Yi Liu wrote: >> Caution: External email. Do not open attachments or click links, >> unless this email comes from a known sender and you know the content >> is safe. >> > Hi, thanks for your review! very efficient! >> >> Hi CMD, >> >> I've went through the series. Some general suggestions on the series. >> >> 1) Patch 01, 02, 04 can be sent separately as they are fixes. > Will do >> 2) This series mixed the ATS and PASID capability a bit. Actually, >> they don't have dependency. I'd suggest you split the series into >> - support ATS for the requests without PASID >> - support ATS for requests with PASID >> The second part should be an incremental change based on the first >> part. If you can make use of the existing translate() callback, then >> it is possible to remove the dependency on Zhenzhong's stage-1 series. > The final purpose is to support SVM, consequently, we only add support > for ATS with PASID here yes. but no need to put all of them in one series. Just like you sent the PRI series separately. >> 3) Some commits do not have commit message. It would be good to have >> it. > Ok, I will be more verbose ;) >> 4) Some helpers look to be used by device model, if possible, it's better >> to submit them with a demo device. > The demo device is already in my GitHub repo > (https://github.com/BullSequana/qemu/tree/master) > It will be sent in a future series that adds the last features required > for SVM (splitting the series to make reviews less painful) >> 5) A design description in the cover-letter would be helpful. > Ok, I will elaborate >> >> On 2024/7/2 13:52, CLEMENT MATHIEU--DRIF wrote: >>> From: Clement Mathieu--Drif >>> >>> This series belongs to a list of series that add SVM support for VT-d. >>> >>> As a starting point, we use the series called 'intel_iommu: Enable >>> stage-1 translation' (rfc2) by Zhenzhong Duan and Yi Liu. >>> >>> Here we focus on the implementation of ATS support in the IOMMU and >>> on a PCI-level >>> API for ATS to be used by virtual devices. >>> >>> This work is based on the VT-d specification version 4.1 (March 2023). >>> Here is a link to a GitHub repository where you can find the >>> following elements : >>> - Qemu with all the patches for SVM >>> - ATS >>> - PRI >>> - Device IOTLB invalidations >>> - Requests with already translated addresses >>> - A demo device >>> - A simple driver for the demo device >>> - A userspace program (for testing and demonstration purposes) >>> >>> https://github.com/BullSequana/Qemu-in-guest-SVM-demo >>> >>> >>> v2 >>> - handle huge pages better by detecting the page table level at >>> which the translation errors occur >>> - Changes after review by ZhenZhong Duan : >>> - Set the access bit after checking permissions >>> - helper for PASID and ATS : make the commit message more >>> accurate ('present' replaced with 'enabled') >>> - pcie_pasid_init: add PCI_PASID_CAP_WIDTH_SHIFT and use it >>> instead of PCI_EXT_CAP_PASID_SIZEOF for shifting the pasid width when >>> preparing the capability register >>> - pci: do not check pci_bus_bypass_iommu after calling >>> pci_device_get_iommu_bus_devfn >>> - do not alter formatting of IOMMUTLBEntry declaration >>> - vtd_iova_fl_check_canonical : directly use s->aw_bits instead >>> of aw for the sake of clarity >>> >>> v3 >>> - rebase on new version of Zhenzhong's flts implementation >>> - fix the atc lookup operation (check the mask before returning >>> an entry) >>> - add a unit test for the ATC >>> - store a user pointer in the iommu notifiers to simplify the >>> implementation of svm devices >>> Changes after review by Zhenzhong : >>> - store the input pasid instead of rid2pasid when returning an >>> entry after a translation >>> - split the ATC implementation and its unit tests >>> >>> v4 >>> Changes after internal review >>> - Fix the nowrite optimization, an ATS translation without the >>> nowrite flag should not fail when the write permission is not set >> >> It's strange to list internal review here. >> >>> v5 >>> Changes after review by Philippe : >>> - change the type of 'level' to unsigned in vtd_lookup_iotlb >> >> list change log from latest to the earliest would be nice too. Look >> forward >> to your next version. :) >> >> Regards, >> Yi Liu >> >>> Clément Mathieu--Drif (22): >>> intel_iommu: fix FRCD construction macro. >>> intel_iommu: make types match >>> intel_iommu: return page walk level even when the translation fails >>> intel_iommu: do not consider wait_desc as an invalid descriptor >>> memory: add permissions in IOMMUAccessFlags >>> pcie: add helper to declare PASID capability for a pcie device >>> pcie: helper functions to check if PASID and ATS are enabled >>> intel_iommu: declare supported PASID size >>> pci: cache the bus mastering status in the device >>> pci: add IOMMU operations to get address spaces and memory regions >>> with PASID >>> memory: store user data pointer in the IOMMU notifiers >>> pci: add a pci-level initialization function for iommu notifiers >>> intel_iommu: implement the get_address_space_pasid iommu operation >>> intel_iommu: implement the get_memory_region_pasid iommu operation >>> memory: Allow to store the PASID in IOMMUTLBEntry >>> intel_iommu: fill the PASID field when creating an instance of >>> IOMMUTLBEntry >>> atc: generic ATC that can be used by PCIe devices that support SVM >>> atc: add unit tests >>> memory: add an API for ATS support >>> pci: add a pci-level API for ATS >>> intel_iommu: set the address mask even when a translation fails >>> intel_iommu: add support for ATS >>> >>> hw/i386/intel_iommu.c | 146 +++++- >>> hw/i386/intel_iommu_internal.h | 6 +- >>> hw/pci/pci.c | 127 +++++- >>> hw/pci/pcie.c | 42 ++ >>> include/exec/memory.h | 51 ++- >>> include/hw/i386/intel_iommu.h | 2 +- >>> include/hw/pci/pci.h | 101 +++++ >>> include/hw/pci/pci_device.h | 1 + >>> include/hw/pci/pcie.h | 9 +- >>> include/hw/pci/pcie_regs.h | 3 + >>> include/standard-headers/linux/pci_regs.h | 1 + >>> system/memory.c | 20 + >>> tests/unit/meson.build | 1 + >>> tests/unit/test-atc.c | 527 ++++++++++++++++++++++ >>> util/atc.c | 211 +++++++++ >>> util/atc.h | 117 +++++ >>> util/meson.build | 1 + >>> 17 files changed, 1332 insertions(+), 34 deletions(-) >>> create mode 100644 tests/unit/test-atc.c >>> create mode 100644 util/atc.c >>> create mode 100644 util/atc.h >>> >> >> -- Regards, Yi Liu