From: Richard Henderson <richard.henderson@linaro.org>
To: Rebecca Cran <rebecca@nuviainc.com>,
Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: Re: [PATCH v3 2/3] target/arm: Add support for FEAT_TLBIOS
Date: Wed, 10 Mar 2021 13:32:36 -0600 [thread overview]
Message-ID: <1c536c6c-792b-9dc5-8bee-57672a42f7ae@linaro.org> (raw)
In-Reply-To: <20210310002917.8876-3-rebecca@nuviainc.com>
On 3/9/21 6:29 PM, Rebecca Cran wrote:
> +static inline bool isar_feature_aa64_tlbios(const ARMISARegisters *id)
> +{
> + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 1 ||
> + FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TLB) == 2;
> +}
The correct test here is != 0. See D13.1.3
Principles of the ID scheme for fields in ID registers.
r~
next prev parent reply other threads:[~2021-03-10 19:37 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-10 0:29 [PATCH v3 0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE Rebecca Cran
2021-03-10 0:29 ` [PATCH v3 1/3] target/arm: Add support for FEAT_TLBIRANGE Rebecca Cran
2021-03-10 19:24 ` Richard Henderson
2021-03-10 21:59 ` Rebecca Cran
2021-03-15 18:34 ` Rebecca Cran
2021-03-15 18:42 ` Richard Henderson
2021-03-16 6:20 ` Rebecca Cran
2021-03-16 15:09 ` Richard Henderson
2021-03-16 15:51 ` Rebecca Cran
2021-03-10 0:29 ` [PATCH v3 2/3] target/arm: Add support for FEAT_TLBIOS Rebecca Cran
2021-03-10 19:32 ` Richard Henderson [this message]
2021-03-10 0:29 ` [PATCH v3 3/3] target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Rebecca Cran
2021-03-10 19:34 ` Richard Henderson
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