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References: <cover.1542321076.git.alistair.francis@wdc.com>
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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Fri, 16 Nov 2018 08:57:06 +0100
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Subject: Re: [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header
 file
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To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>

On 11/15/18 11:34 PM, Alistair Francis wrote:
> +#define TCG_TARGET_HAS_add2_i32         0
> +#define TCG_TARGET_HAS_sub2_i32         0

You're not allowed to not implement this for riscv-32,
along with brcond2 and setcond2.

> +#define TCG_TARGET_HAS_movcond_i32      0

The architecture manual suggests that implementations recognize short
branch-over and convert internally to predication.  Do any do that?

Even if they don't, you might implement it that way anyway, as the code size
savings are large vs the inline fallback (6 insns).  But you can definitely put
that off for a later patch.

> +#define TCG_TARGET_HAS_ext16u_i32       1

Really?  I thought this required two insns...  Or do you expand to shifts while
the default is x & 0xffff, which would take 3 insns?  I guess I'll find out as
I keep reading.  ;-)


r~