From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com
Subject: Re: [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b
Date: Thu, 25 Jul 2024 12:45:18 +1000 [thread overview]
Message-ID: <1c82060a-4352-497b-818e-767c1ceb73df@linaro.org> (raw)
In-Reply-To: <5c34fb1a-ce46-4039-b887-9ea56488239b@linux.alibaba.com>
On 7/24/24 16:32, LIU Zhiwei wrote:
>> However! It does explicitly say "no more than MXLEN bits", which means that an RV32/
>> RV64 check is appropriate for FLD/FSD, since MXLEN may be less than 64.
> Yes. That's true. Although I don't know why MXLEN is needed as F, D or Q don't depend on
> MXLEN. We can implement D extension on RV32 CPU.
Implementation of D on RV32 does not mean that FLD/FST is atomic -- it can be implemented
with two 32-bit loads/stores under the hood.
r~
next prev parent reply other threads:[~2024-07-25 2:46 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-23 1:30 [PATCH 1/1] target/riscv: Remove redundant insn length check for zama16b LIU Zhiwei
2024-07-23 2:11 ` Richard Henderson
2024-07-23 3:50 ` Alistair Francis
2024-07-23 5:29 ` LIU Zhiwei
2024-07-23 5:59 ` Richard Henderson
2024-07-24 6:32 ` LIU Zhiwei
2024-07-25 2:45 ` Richard Henderson [this message]
2024-07-25 1:50 ` LIU Zhiwei
2024-07-31 9:38 ` Alistair Francis
2024-07-31 11:21 ` LIU Zhiwei
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