From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v6 11/16] target/riscv: mmu changes for zicfiss shadow stack protection
Date: Thu, 22 Aug 2024 10:30:05 +1000 [thread overview]
Message-ID: <1cb8d332-4092-4a2d-be24-01280f91cb8c@linaro.org> (raw)
In-Reply-To: <20240821215014.3859190-12-debug@rivosinc.com>
On 8/22/24 07:50, Deepak Gupta wrote:
> zicfiss protects shadow stack using new page table encodings PTE.W=0,
> PTE.R=0 and PTE.X=0. This encoding is reserved if zicfiss is not
> implemented or if shadow stack are not enabled.
> Loads on shadow stack memory are allowed while stores to shadow stack
> memory leads to access faults. Shadow stack accesses to RO memory
> leads to store page fault.
>
> To implement special nature of shadow stack memory where only selected
> stores (shadow stack stores from sspush) have to be allowed while rest
> of regular stores disallowed, new MMU TLB index is created for shadow
> stack.
>
> Signed-off-by: Deepak Gupta<debug@rivosinc.com>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> ---
> target/riscv/cpu_helper.c | 37 +++++++++++++++++++++++++++++++------
> target/riscv/internals.h | 3 +++
> 2 files changed, 34 insertions(+), 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2024-08-22 0:30 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-21 21:49 [PATCH v6 00/16] riscv support for control flow integrity extensions Deepak Gupta
2024-08-21 21:49 ` [PATCH v6 01/16] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 02/16] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 03/16] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 04/16] target/riscv: additional code information for sw check Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 05/16] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-22 0:25 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 06/16] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 07/16] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 08/16] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 09/16] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-22 0:27 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 10/16] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 11/16] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-22 0:30 ` Richard Henderson [this message]
2024-08-21 21:50 ` [PATCH v6 12/16] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-22 0:43 ` Richard Henderson
2024-08-22 0:58 ` Deepak Gupta
2024-08-22 5:13 ` Richard Henderson
2024-08-21 21:50 ` [PATCH v6 13/16] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-22 0:57 ` Richard Henderson
2024-08-22 1:00 ` Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 14/16] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 15/16] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-21 21:50 ` [PATCH v6 16/16] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1cb8d332-4092-4a2d-be24-01280f91cb8c@linaro.org \
--to=richard.henderson@linaro.org \
--cc=Alistair.Francis@wdc.com \
--cc=andy.chiu@sifive.com \
--cc=bmeng.cn@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=debug@rivosinc.com \
--cc=jim.shu@sifive.com \
--cc=kito.cheng@sifive.com \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).