From: Richard Henderson <richard.henderson@linaro.org>
To: "Frédéric Pétrot" <frederic.petrot@univ-grenoble-alpes.fr>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: philmd@redhat.com, bin.meng@windriver.com,
alistair.francis@wdc.com, palmer@dabbelt.com,
fabien.portas@grenoble-inp.org
Subject: Re: [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions
Date: Sat, 30 Oct 2021 21:03:34 -0700 [thread overview]
Message-ID: <1cbc85e2-8c83-c8f9-651c-9b49bfd923f0@linaro.org> (raw)
In-Reply-To: <20211025122818.168890-12-frederic.petrot@univ-grenoble-alpes.fr>
On 10/25/21 5:28 AM, Frédéric Pétrot wrote:
> + if (get_xl(ctx) < MXL_RV128 || max_len < 128) {
Only the second test is required; the first is redundant.
> static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
> - void (*func)(TCGv, TCGv, TCGv))
> + void (*func)(TCGv, TCGv, TCGv),
> + void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv))
> {
> - TCGv dest = dest_gpr(ctx, a->rd);
> - TCGv src1 = get_gpr(ctx, a->rs1, ext);
> TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> TCGv ext2 = tcg_temp_new();
>
> tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1);
> - func(dest, src1, ext2);
>
> - gen_set_gpr(ctx, a->rd, dest);
> + TCGv dest = dest_gpr(ctx, a->rd);
> + TCGv src1 = get_gpr(ctx, a->rs1, ext);
> +
> + if (get_xl(ctx) < MXL_RV128 || get_ol(ctx) < MXL_RV128) {
Again, only one test; probably better pulling out max_len, like we did above, since now we
query OL twice.
> +}
> +
> +
Careful with the extra lines.
r~
next prev parent reply other threads:[~2021-10-31 4:05 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-25 12:28 [PATCH v4 00/17] Adding partial support for 128-bit riscv target Frédéric Pétrot
2021-10-25 12:28 ` [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO Frédéric Pétrot
2021-10-25 20:09 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations Frédéric Pétrot
2021-10-25 15:47 ` Philippe Mathieu-Daudé
2021-10-25 20:16 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 03/17] target/riscv: additional macros to check instruction support Frédéric Pétrot
2021-10-30 23:49 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers Frédéric Pétrot
2021-10-25 15:51 ` Philippe Mathieu-Daudé
2021-10-25 19:08 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers Frédéric Pétrot
2021-10-25 15:55 ` Philippe Mathieu-Daudé
2021-10-25 19:10 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles Frédéric Pétrot
2021-10-30 23:52 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 07/17] target/riscv: moving some insns close to similar insns Frédéric Pétrot
2021-10-25 15:56 ` Philippe Mathieu-Daudé
2021-10-25 12:28 ` [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store Frédéric Pétrot
2021-10-31 3:41 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions Frédéric Pétrot
2021-10-31 3:44 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions Frédéric Pétrot
2021-10-31 3:49 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 11/17] target/riscv: support for 128-bit shift instructions Frédéric Pétrot
2021-10-31 4:03 ` Richard Henderson [this message]
2021-10-25 12:28 ` [PATCH v4 12/17] target/riscv: support for 128-bit arithmetic instructions Frédéric Pétrot
2021-11-02 12:43 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 13/17] target/riscv: support for 128-bit M extension Frédéric Pétrot
2021-11-02 13:05 ` Richard Henderson
2021-10-25 12:28 ` [PATCH v4 14/17] target/riscv: adding high part of some csrs Frédéric Pétrot
2021-10-25 12:28 ` [PATCH v4 15/17] target/riscv: helper functions to wrap calls to 128-bit csr insns Frédéric Pétrot
2021-10-25 12:28 ` [PATCH v4 16/17] target/riscv: modification of the trans_csrxx for 128-bit support Frédéric Pétrot
2021-10-25 12:28 ` [PATCH v4 17/17] target/riscv: actual functions to realize crs 128-bit insns Frédéric Pétrot
2021-11-02 13:22 ` Richard Henderson
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