From: Richard Henderson <richard.henderson@linaro.org>
To: Nick Bowler <nbowler@draconx.ca>, qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Artyom Tarasenko <atar4qemu@gmail.com>
Subject: Re: [PATCH 2/8] target/sparc: Fix VIS fmul8x16au instruction.
Date: Thu, 28 Sep 2023 14:32:43 -0700 [thread overview]
Message-ID: <1cd9adb3-004c-7512-e587-085959296f03@linaro.org> (raw)
In-Reply-To: <20230925050545.30912-3-nbowler@draconx.ca>
On 9/24/23 01:03, Nick Bowler wrote:
> On a real UltraSparc II, the fmul8x16au instruction takes two single-
> precision input operands and returns a double-precision result. For
> the second operand, bits 31:16 are used, and bits 15:0 are ignored.
>
> However, the emulation is taking two double-precision input operands,
> and furthermore it is using bits 15:0 of the second operand (ignoring
> bits 31:16). These are unlikely to contain the correct values.
>
> Even still, the emulator overwrites the second input before all outputs
> are calculated, so even if by chance the data loaded in happens to be
> correct, the results are just garbage except in trivial cases.
>
> Signed-off-by: Nick Bowler <nbowler@draconx.ca>
> ---
> target/sparc/helper.h | 2 +-
> target/sparc/translate.c | 19 ++++++++++++++++++-
> target/sparc/vis_helper.c | 14 +++++++++-----
> 3 files changed, 28 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> #define PMUL(r) \
> - tmp = (int32_t)d.VIS_SW64(0) * (int32_t)s.VIS_B64(r); \
> + tmp = (int32_t)s2.VIS_SW32(1) * (int32_t)s1.VIS_B64(r); \
> if ((tmp & 0xff) > 0x7f) { \
> tmp += 0x100; \
> } \
Belated follow-up suggestion:
- if ((tmp & 0xff) > 0x7f) {
- tmp += 0x100;
- }
+ tmp += 0x80;
7 occurrences throughout vis_helper.c.
r~
next prev parent reply other threads:[~2023-09-28 21:33 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-25 5:03 [PATCH 0/8] SPARC VIS fixes Nick Bowler
2023-09-25 5:03 ` [PATCH 1/8] target/sparc: Fix VIS fmul8x16 input register Nick Bowler
2023-09-28 21:29 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 2/8] target/sparc: Fix VIS fmul8x16au instruction Nick Bowler
2023-09-28 21:32 ` Richard Henderson [this message]
2023-09-29 0:41 ` Nick Bowler
2023-09-29 1:04 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 3/8] target/sparc: Fix VIS fmul8x16al instruction Nick Bowler
2023-09-28 21:32 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 4/8] target/sparc: Fix VIS fmuld8sux16 instruction Nick Bowler
2023-09-28 21:33 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 5/8] target/sparc: Fix VIS fmuld8ulx16 instruction Nick Bowler
2023-09-28 21:34 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 6/8] target/sparc: Fix VIS fpmerge input registers Nick Bowler
2023-09-28 21:35 ` Richard Henderson
2023-09-29 0:32 ` Nick Bowler
2023-09-25 5:03 ` [PATCH 7/8] target/sparc: Fix VIS fexpand input register Nick Bowler
2023-09-28 21:36 ` Richard Henderson
2023-09-25 5:03 ` [PATCH 8/8] target/sparc: Fix VIS subtraction instructions Nick Bowler
2023-09-28 21:40 ` Richard Henderson
2023-09-29 0:31 ` Nick Bowler
2023-09-28 20:05 ` [PATCH 0/8] SPARC VIS fixes Mark Cave-Ayland
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