[PATCH 00/11] enable write_misa() and RISCV_FEATURE_* cleanups

[PATCH 00/11] enable write_misa() and RISCV_FEATURE_* cleanups

[Daniel Henrique Barboza]

Hi,

Initially this was supposed to be just the first 2 patches, where we
enable users to be able to actually write the MISA CSR (yes, at this
moment all the code in write_misa() is a no-op).

During an internal discussion of that code, Andrew Jones pointed out
that I was setting RISCV_FEATURE_MISA by just mirroring the value
already set in cpu->cfg.misa_w, and asked why that was necessary.
Instead of replying "I'm doing it because it's being done for every
other feature in that enum" - which was the truth - I decided to take a
closer look.

The RISCV_FEATURES_* enum and the CPUArchState::features attribute were
introduced 4+ years ago, as a way to retrieve the enabled hart features
that aren't represented via MISA CSR bits. Time passed on, and
RISCVCPUConfig was introduced. With it, we now have a centralized way of
reading all hart features that are enabled/disabled by the user and the
board. All recent features are reading their correspondent cpu->cfg.X
flag.

All but the 5 features in the RISCV_FEATURE_* enum. These features are
still operating in the same way: set it during riscv_cpu_realize() using
their cpu->cfg value, read it using riscv_feature() when needed. There
is nothing special about them in comparison with all the other features
and extensions to justify this special handling.

This series then is doing two things: first we're actually allowing
users to write the MISA CSR if they so choose. Then we're deprecate each
RISC_FEATURE_* usage until, in patch 11, we remove everything related to
it. All 5 existing RISCV_FEATURE_* features will be handled as everyone
else. 

Note: patch 6 is adding an error message that will fire a checkpatch.pl
warning (82 chars). The following patch will put the error message back
into the acceptable 80 chars range. 

Daniel Henrique Barboza (11):
  target/riscv: do not mask unsupported QEMU extensions in write_misa()
  target/riscv: allow users to actually write the MISA CSR
  target/riscv: remove RISCV_FEATURE_MISA
  target/riscv: introduce riscv_cpu_cfg()
  target/riscv: remove RISCV_FEATURE_DEBUG
  target/riscv/cpu.c: error out if EPMP is enabled without PMP
  target/riscv: remove RISCV_FEATURE_EPMP
  target/riscv: remove RISCV_FEATURE_PMP
  hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in
    create_fdt_socket_cpus()
  target/riscv: remove RISCV_FEATURE_MMU
  target/riscv/cpu: remove CPUArchState::features and friends

 hw/riscv/virt.c           |  7 ++++---
 target/riscv/cpu.c        | 20 +++++---------------
 target/riscv/cpu.h        | 29 ++++++-----------------------
 target/riscv/cpu_helper.c |  6 +++---
 target/riscv/csr.c        | 17 ++++++++---------
 target/riscv/machine.c    | 11 ++++-------
 target/riscv/monitor.c    |  2 +-
 target/riscv/op_helper.c  |  2 +-
 target/riscv/pmp.c        |  8 ++++----
 9 files changed, 36 insertions(+), 66 deletions(-)

-- 
2.39.1

[PATCH 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa()

[Daniel Henrique Barboza]

The masking done using env->misa_ext_mask already filters any extension
that QEMU doesn't support. If the hart supports the extension then QEMU
supports it as well.

If the masking done by env->misa_ext_mask is somehow letting unsupported
QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/csr.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1b0a0c1693..e149b453da 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
     /* Mask extensions that are not supported by this hart */
     val &= env->misa_ext_mask;
 
-    /* Mask extensions that are not supported by QEMU */
-    val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
-
     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
     if ((val & RVD) && !(val & RVF)) {
         val &= ~RVD;
-- 
2.39.1

Re: [PATCH 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa()

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> The masking done using env->misa_ext_mask already filters any extension
> that QEMU doesn't support. If the hart supports the extension then QEMU
> supports it as well.
>
> If the masking done by env->misa_ext_mask is somehow letting unsupported
> QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li
> ---
>   target/riscv/csr.c | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 1b0a0c1693..e149b453da 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1356,9 +1356,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
>       /* Mask extensions that are not supported by this hart */
>       val &= env->misa_ext_mask;
>   
> -    /* Mask extensions that are not supported by QEMU */
> -    val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
> -
>       /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
>       if ((val & RVD) && !(val & RVF)) {
>           val &= ~RVD;

[PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

[Daniel Henrique Barboza]

At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well because write_misa() will always exit
earlier.

This seems to be benign in the majority of cases. Booting an Ubuntu
'virt' guest and logging all the calls to 'write_misa' shows that no
writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
RISC-V extensions after the machine is powered on, seems to be a niche
use.

There is a good chance that the code in write_misa() hasn't been
properly tested. Allowing users to write MISA can open the floodgates of
new breeds of bugs. We could instead remove most (if not all) of
write_misa() since it's never used. Well, as a hardware emulator,
dealing with crashes because a register write went wrong is what we're
here for.

Create a 'misa-w' CPU property to allow users to choose whether writes
to MISA should be allowed. The default is set to 'false' for all RISC-V
machines to keep compatibility with what we´ve been doing so far.

Read cpu->cfg.misa_w directly in write_misa(), instead of executing
riscv_set_feature(RISCV_FEATURE_MISA) in riscv_cpu_realize(), that would
simply reflect the cpu->cfg.misa_w bool value in 'env->features' and
require a riscv_feature() call to read it back.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 1 +
 target/riscv/cpu.h | 1 +
 target/riscv/csr.c | 4 +++-
 3 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..69fb9e123f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1197,6 +1197,7 @@ static void register_cpu_props(DeviceState *dev)
 
 static Property riscv_cpu_properties[] = {
     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+    DEFINE_PROP_BOOL("misa-w", RISCVCPU, cfg.misa_w, false),
 
     DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
     DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7128438d8e..103963b386 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -498,6 +498,7 @@ struct RISCVCPUConfig {
     bool pmp;
     bool epmp;
     bool debug;
+    bool misa_w;
 
     bool short_isa_string;
 };
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e149b453da..4f9cc501b2 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1329,7 +1329,9 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
 static RISCVException write_misa(CPURISCVState *env, int csrno,
                                  target_ulong val)
 {
-    if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
+    RISCVCPU *cpu = env_archcpu(env);
+
+    if (!cpu->cfg.misa_w) {
         /* drop write to misa */
         return RISCV_EXCP_NONE;
     }
-- 
2.39.1

Re: [PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> At this moment, and apparently since ever, we have no way of enabling
> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
> the nuts and bolts that handles how to properly write this CSR, has
> always been a no-op as well because write_misa() will always exit
> earlier.
>
> This seems to be benign in the majority of cases. Booting an Ubuntu
> 'virt' guest and logging all the calls to 'write_misa' shows that no
> writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
> RISC-V extensions after the machine is powered on, seems to be a niche
> use.
>
> There is a good chance that the code in write_misa() hasn't been
> properly tested. Allowing users to write MISA can open the floodgates of
> new breeds of bugs. We could instead remove most (if not all) of
> write_misa() since it's never used. Well, as a hardware emulator,
> dealing with crashes because a register write went wrong is what we're
> here for.
>
> Create a 'misa-w' CPU property to allow users to choose whether writes
> to MISA should be allowed. The default is set to 'false' for all RISC-V
> machines to keep compatibility with what we´ve been doing so far.
>
> Read cpu->cfg.misa_w directly in write_misa(), instead of executing
> riscv_set_feature(RISCV_FEATURE_MISA) in riscv_cpu_realize(), that would
> simply reflect the cpu->cfg.misa_w bool value in 'env->features' and
> require a riscv_feature() call to read it back.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   target/riscv/cpu.c | 1 +
>   target/riscv/cpu.h | 1 +
>   target/riscv/csr.c | 4 +++-
>   3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 93b52b826c..69fb9e123f 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1197,6 +1197,7 @@ static void register_cpu_props(DeviceState *dev)
>   
>   static Property riscv_cpu_properties[] = {
>       DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
> +    DEFINE_PROP_BOOL("misa-w", RISCVCPU, cfg.misa_w, false),
>   
>       DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
>       DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 7128438d8e..103963b386 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -498,6 +498,7 @@ struct RISCVCPUConfig {
>       bool pmp;
>       bool epmp;
>       bool debug;
> +    bool misa_w;
>   
>       bool short_isa_string;
>   };
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index e149b453da..4f9cc501b2 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1329,7 +1329,9 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
>   static RISCVException write_misa(CPURISCVState *env, int csrno,
>                                    target_ulong val)
>   {
> -    if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
> +    RISCVCPU *cpu = env_archcpu(env);
> +
> +    if (!cpu->cfg.misa_w) {

It's Ok to get it directly from cfg. However, personally, I prefer to 
keep the non-isa features in a separate list.

Regards,

Weiwei Li

>           /* drop write to misa */
>           return RISCV_EXCP_NONE;
>       }

Re: [PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

[Daniel Henrique Barboza]

On 2/10/23 23:43, weiwei wrote:
> 
> On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
>> At this moment, and apparently since ever, we have no way of enabling
>> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
>> the nuts and bolts that handles how to properly write this CSR, has
>> always been a no-op as well because write_misa() will always exit
>> earlier.
>>
>> This seems to be benign in the majority of cases. Booting an Ubuntu
>> 'virt' guest and logging all the calls to 'write_misa' shows that no
>> writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
>> RISC-V extensions after the machine is powered on, seems to be a niche
>> use.
>>
>> There is a good chance that the code in write_misa() hasn't been
>> properly tested. Allowing users to write MISA can open the floodgates of
>> new breeds of bugs. We could instead remove most (if not all) of
>> write_misa() since it's never used. Well, as a hardware emulator,
>> dealing with crashes because a register write went wrong is what we're
>> here for.
>>
>> Create a 'misa-w' CPU property to allow users to choose whether writes
>> to MISA should be allowed. The default is set to 'false' for all RISC-V
>> machines to keep compatibility with what we´ve been doing so far.
>>
>> Read cpu->cfg.misa_w directly in write_misa(), instead of executing
>> riscv_set_feature(RISCV_FEATURE_MISA) in riscv_cpu_realize(), that would
>> simply reflect the cpu->cfg.misa_w bool value in 'env->features' and
>> require a riscv_feature() call to read it back.
>>
>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>> ---
>>   target/riscv/cpu.c | 1 +
>>   target/riscv/cpu.h | 1 +
>>   target/riscv/csr.c | 4 +++-
>>   3 files changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 93b52b826c..69fb9e123f 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -1197,6 +1197,7 @@ static void register_cpu_props(DeviceState *dev)
>>   static Property riscv_cpu_properties[] = {
>>       DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>> +    DEFINE_PROP_BOOL("misa-w", RISCVCPU, cfg.misa_w, false),
>>       DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
>>       DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>> index 7128438d8e..103963b386 100644
>> --- a/target/riscv/cpu.h
>> +++ b/target/riscv/cpu.h
>> @@ -498,6 +498,7 @@ struct RISCVCPUConfig {
>>       bool pmp;
>>       bool epmp;
>>       bool debug;
>> +    bool misa_w;
>>       bool short_isa_string;
>>   };
>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>> index e149b453da..4f9cc501b2 100644
>> --- a/target/riscv/csr.c
>> +++ b/target/riscv/csr.c
>> @@ -1329,7 +1329,9 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
>>   static RISCVException write_misa(CPURISCVState *env, int csrno,
>>                                    target_ulong val)
>>   {
>> -    if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
>> +    RISCVCPU *cpu = env_archcpu(env);
>> +
>> +    if (!cpu->cfg.misa_w) {
> 
> It's Ok to get it directly from cfg. However, personally, I prefer to keep the non-isa features in a separate list.

I don't mind a separated non-isa list. cpu->cfg has everything contained in it
though, ISA and non-ISA (e.g. vendor extensions that weren't ratified yet), and
the current RISCV_FEATURES_* list is just a duplicate of it that we need to
update it during riscv_cpu_realize().

In my opinion we can spare the extra effort of keeping a separated, up-to-date
non-ISA extension/features list, by just reading everything from cfg.


Thanks,


Daniel

> 
> Regards,
> 
> Weiwei Li
> 
>>           /* drop write to misa */
>>           return RISCV_EXCP_NONE;
>>       }
> 

Re: [PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

[weiwei]

On 2023/2/11 19:50, Daniel Henrique Barboza wrote:
>
>
> On 2/10/23 23:43, weiwei wrote:
>>
>> On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
>>> At this moment, and apparently since ever, we have no way of enabling
>>> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
>>> the nuts and bolts that handles how to properly write this CSR, has
>>> always been a no-op as well because write_misa() will always exit
>>> earlier.
>>>
>>> This seems to be benign in the majority of cases. Booting an Ubuntu
>>> 'virt' guest and logging all the calls to 'write_misa' shows that no
>>> writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
>>> RISC-V extensions after the machine is powered on, seems to be a niche
>>> use.
>>>
>>> There is a good chance that the code in write_misa() hasn't been
>>> properly tested. Allowing users to write MISA can open the 
>>> floodgates of
>>> new breeds of bugs. We could instead remove most (if not all) of
>>> write_misa() since it's never used. Well, as a hardware emulator,
>>> dealing with crashes because a register write went wrong is what we're
>>> here for.
>>>
>>> Create a 'misa-w' CPU property to allow users to choose whether writes
>>> to MISA should be allowed. The default is set to 'false' for all RISC-V
>>> machines to keep compatibility with what we´ve been doing so far.
>>>
>>> Read cpu->cfg.misa_w directly in write_misa(), instead of executing
>>> riscv_set_feature(RISCV_FEATURE_MISA) in riscv_cpu_realize(), that 
>>> would
>>> simply reflect the cpu->cfg.misa_w bool value in 'env->features' and
>>> require a riscv_feature() call to read it back.
>>>
>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>> ---
>>>   target/riscv/cpu.c | 1 +
>>>   target/riscv/cpu.h | 1 +
>>>   target/riscv/csr.c | 4 +++-
>>>   3 files changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>> index 93b52b826c..69fb9e123f 100644
>>> --- a/target/riscv/cpu.c
>>> +++ b/target/riscv/cpu.c
>>> @@ -1197,6 +1197,7 @@ static void register_cpu_props(DeviceState *dev)
>>>   static Property riscv_cpu_properties[] = {
>>>       DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>>> +    DEFINE_PROP_BOOL("misa-w", RISCVCPU, cfg.misa_w, false),
>>>       DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
>>>       DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, 
>>> RISCV_CPU_MARCHID),
>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>> index 7128438d8e..103963b386 100644
>>> --- a/target/riscv/cpu.h
>>> +++ b/target/riscv/cpu.h
>>> @@ -498,6 +498,7 @@ struct RISCVCPUConfig {
>>>       bool pmp;
>>>       bool epmp;
>>>       bool debug;
>>> +    bool misa_w;
>>>       bool short_isa_string;
>>>   };
>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>> index e149b453da..4f9cc501b2 100644
>>> --- a/target/riscv/csr.c
>>> +++ b/target/riscv/csr.c
>>> @@ -1329,7 +1329,9 @@ static RISCVException read_misa(CPURISCVState 
>>> *env, int csrno,
>>>   static RISCVException write_misa(CPURISCVState *env, int csrno,
>>>                                    target_ulong val)
>>>   {
>>> -    if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
>>> +    RISCVCPU *cpu = env_archcpu(env);
>>> +
>>> +    if (!cpu->cfg.misa_w) {
>>
>> It's Ok to get it directly from cfg. However, personally, I prefer to 
>> keep the non-isa features in a separate list.
>
> I don't mind a separated non-isa list. cpu->cfg has everything 
> contained in it
> though, ISA and non-ISA (e.g. vendor extensions that weren't ratified 
> yet), and
> the current RISCV_FEATURES_* list is just a duplicate of it that we 
> need to
> update it during riscv_cpu_realize().
>
> In my opinion we can spare the extra effort of keeping a separated, 
> up-to-date
> non-ISA extension/features list, by just reading everything from cfg.
>
>
> Thanks,
>
>
> Daniel

OK. It's  acceptable to me.

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

By the way, the riscv_cpu_cfg() in patch 4 can be used here.

Regards,

Weiwei Li

>
>>
>> Regards,
>>
>> Weiwei Li
>>
>>>           /* drop write to misa */
>>>           return RISCV_EXCP_NONE;
>>>       }
>>

Re: [PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

[Daniel Henrique Barboza]

On 2/14/23 12:12, weiwei wrote:
> 
> On 2023/2/11 19:50, Daniel Henrique Barboza wrote:
>>
>>
>> On 2/10/23 23:43, weiwei wrote:
>>>
>>> On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
>>>> At this moment, and apparently since ever, we have no way of enabling
>>>> RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
>>>> the nuts and bolts that handles how to properly write this CSR, has
>>>> always been a no-op as well because write_misa() will always exit
>>>> earlier.
>>>>
>>>> This seems to be benign in the majority of cases. Booting an Ubuntu
>>>> 'virt' guest and logging all the calls to 'write_misa' shows that no
>>>> writes to MISA CSR was attempted. Writing MISA, i.e. enabling/disabling
>>>> RISC-V extensions after the machine is powered on, seems to be a niche
>>>> use.
>>>>
>>>> There is a good chance that the code in write_misa() hasn't been
>>>> properly tested. Allowing users to write MISA can open the floodgates of
>>>> new breeds of bugs. We could instead remove most (if not all) of
>>>> write_misa() since it's never used. Well, as a hardware emulator,
>>>> dealing with crashes because a register write went wrong is what we're
>>>> here for.
>>>>
>>>> Create a 'misa-w' CPU property to allow users to choose whether writes
>>>> to MISA should be allowed. The default is set to 'false' for all RISC-V
>>>> machines to keep compatibility with what we´ve been doing so far.
>>>>
>>>> Read cpu->cfg.misa_w directly in write_misa(), instead of executing
>>>> riscv_set_feature(RISCV_FEATURE_MISA) in riscv_cpu_realize(), that would
>>>> simply reflect the cpu->cfg.misa_w bool value in 'env->features' and
>>>> require a riscv_feature() call to read it back.
>>>>
>>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
>>>> ---
>>>>   target/riscv/cpu.c | 1 +
>>>>   target/riscv/cpu.h | 1 +
>>>>   target/riscv/csr.c | 4 +++-
>>>>   3 files changed, 5 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>>>> index 93b52b826c..69fb9e123f 100644
>>>> --- a/target/riscv/cpu.c
>>>> +++ b/target/riscv/cpu.c
>>>> @@ -1197,6 +1197,7 @@ static void register_cpu_props(DeviceState *dev)
>>>>   static Property riscv_cpu_properties[] = {
>>>>       DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
>>>> +    DEFINE_PROP_BOOL("misa-w", RISCVCPU, cfg.misa_w, false),
>>>>       DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
>>>>       DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
>>>> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
>>>> index 7128438d8e..103963b386 100644
>>>> --- a/target/riscv/cpu.h
>>>> +++ b/target/riscv/cpu.h
>>>> @@ -498,6 +498,7 @@ struct RISCVCPUConfig {
>>>>       bool pmp;
>>>>       bool epmp;
>>>>       bool debug;
>>>> +    bool misa_w;
>>>>       bool short_isa_string;
>>>>   };
>>>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
>>>> index e149b453da..4f9cc501b2 100644
>>>> --- a/target/riscv/csr.c
>>>> +++ b/target/riscv/csr.c
>>>> @@ -1329,7 +1329,9 @@ static RISCVException read_misa(CPURISCVState *env, int csrno,
>>>>   static RISCVException write_misa(CPURISCVState *env, int csrno,
>>>>                                    target_ulong val)
>>>>   {
>>>> -    if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
>>>> +    RISCVCPU *cpu = env_archcpu(env);
>>>> +
>>>> +    if (!cpu->cfg.misa_w) {
>>>
>>> It's Ok to get it directly from cfg. However, personally, I prefer to keep the non-isa features in a separate list.
>>
>> I don't mind a separated non-isa list. cpu->cfg has everything contained in it
>> though, ISA and non-ISA (e.g. vendor extensions that weren't ratified yet), and
>> the current RISCV_FEATURES_* list is just a duplicate of it that we need to
>> update it during riscv_cpu_realize().
>>
>> In my opinion we can spare the extra effort of keeping a separated, up-to-date
>> non-ISA extension/features list, by just reading everything from cfg.
>>
>>
>> Thanks,
>>
>>
>> Daniel
> 
> OK. It's  acceptable to me.
> 
> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
> 
> By the way, the riscv_cpu_cfg() in patch 4 can be used here.

Good point. I'll move patch 4 up so I can use that function here.



Daniel

> 
> Regards,
> 
> Weiwei Li
> 
>>
>>>
>>> Regards,
>>>
>>> Weiwei Li
>>>
>>>>           /* drop write to misa */
>>>>           return RISCV_EXCP_NONE;
>>>>       }
>>>
> 

[PATCH 03/11] target/riscv: remove RISCV_FEATURE_MISA

[Daniel Henrique Barboza]

This enum is no longer used after write_misa() started reading the value
from cpu->cfg.misa_w.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 103963b386..6509ffa951 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -89,7 +89,6 @@ enum {
     RISCV_FEATURE_MMU,
     RISCV_FEATURE_PMP,
     RISCV_FEATURE_EPMP,
-    RISCV_FEATURE_MISA,
     RISCV_FEATURE_DEBUG
 };
 
-- 
2.39.1

Re: [PATCH 03/11] target/riscv: remove RISCV_FEATURE_MISA

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> This enum is no longer used after write_misa() started reading the value
> from cpu->cfg.misa_w.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>r

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.h | 1 -
>   1 file changed, 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 103963b386..6509ffa951 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -89,7 +89,6 @@ enum {
>       RISCV_FEATURE_MMU,
>       RISCV_FEATURE_PMP,
>       RISCV_FEATURE_EPMP,
> -    RISCV_FEATURE_MISA,
>       RISCV_FEATURE_DEBUG
>   };
>   

[PATCH 04/11] target/riscv: introduce riscv_cpu_cfg()

[Daniel Henrique Barboza]

We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6509ffa951..00a464c9c4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
 #endif
 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
 
+static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env)
+{
+    return env_archcpu(env)->cfg;
+}
+
 #if defined(TARGET_RISCV32)
 #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
 #else
-- 
2.39.1

Re: [PATCH 04/11] target/riscv: introduce riscv_cpu_cfg()

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> We're going to do changes that requires accessing the RISCVCPUConfig
> struct from the RISCVCPU, having access only to a CPURISCVState 'env'
> pointer. Add a helper to make the code easier to read.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.h | 5 +++++
>   1 file changed, 5 insertions(+)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 6509ffa951..00a464c9c4 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -654,6 +654,11 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
>   #endif
>   #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
>   
> +static inline RISCVCPUConfig riscv_cpu_cfg(CPURISCVState *env)
> +{
> +    return env_archcpu(env)->cfg;
> +}
> +
>   #if defined(TARGET_RISCV32)
>   #define cpu_recompute_xl(env)  ((void)(env), MXL_RV32)
>   #else

[PATCH 05/11] target/riscv: remove RISCV_FEATURE_DEBUG

[Daniel Henrique Barboza]

RISCV_FEATURE_DEBUG will always follow the value defined by
cpu->cfg.debug flag. Read the flag instead.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c        | 6 +-----
 target/riscv/cpu.h        | 1 -
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 2 +-
 target/riscv/machine.c    | 3 +--
 5 files changed, 4 insertions(+), 10 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 69fb9e123f..272cf1a8bf 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj)
     set_default_nan_mode(1, &env->fp_status);
 
 #ifndef CONFIG_USER_ONLY
-    if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+    if (cpu->cfg.debug) {
         riscv_trigger_init(env);
     }
 
@@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
     }
 
-    if (cpu->cfg.debug) {
-        riscv_set_feature(env, RISCV_FEATURE_DEBUG);
-    }
-
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->cfg.ext_sstc) {
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 00a464c9c4..46de6f2f7f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -89,7 +89,6 @@ enum {
     RISCV_FEATURE_MMU,
     RISCV_FEATURE_PMP,
     RISCV_FEATURE_EPMP,
-    RISCV_FEATURE_DEBUG
 };
 
 /* Privileged specification version */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ad8d82662c..4cdd247c6c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
         flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
                            get_field(env->mstatus_hs, MSTATUS_VS));
     }
-    if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
+    if (cpu->cfg.debug && !icount_enabled()) {
         flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
     }
 #endif
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4f9cc501b2..af4a44b33b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
 
 static RISCVException debug(CPURISCVState *env, int csrno)
 {
-    if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+    if (riscv_cpu_cfg(env).debug) {
         return RISCV_EXCP_NONE;
     }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index c6ce318cce..4634968898 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = {
 static bool debug_needed(void *opaque)
 {
     RISCVCPU *cpu = opaque;
-    CPURISCVState *env = &cpu->env;
 
-    return riscv_feature(env, RISCV_FEATURE_DEBUG);
+    return cpu->cfg.debug;
 }
 
 static int debug_post_load(void *opaque, int version_id)
-- 
2.39.1

Re: [PATCH 05/11] target/riscv: remove RISCV_FEATURE_DEBUG

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> RISCV_FEATURE_DEBUG will always follow the value defined by
> cpu->cfg.debug flag. Read the flag instead.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.c        | 6 +-----
>   target/riscv/cpu.h        | 1 -
>   target/riscv/cpu_helper.c | 2 +-
>   target/riscv/csr.c        | 2 +-
>   target/riscv/machine.c    | 3 +--
>   5 files changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 69fb9e123f..272cf1a8bf 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj)
>       set_default_nan_mode(1, &env->fp_status);
>   
>   #ifndef CONFIG_USER_ONLY
> -    if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
> +    if (cpu->cfg.debug) {
>           riscv_trigger_init(env);
>       }
>   
> @@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>           }
>       }
>   
> -    if (cpu->cfg.debug) {
> -        riscv_set_feature(env, RISCV_FEATURE_DEBUG);
> -    }
> -
>   
>   #ifndef CONFIG_USER_ONLY
>       if (cpu->cfg.ext_sstc) {
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 00a464c9c4..46de6f2f7f 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -89,7 +89,6 @@ enum {
>       RISCV_FEATURE_MMU,
>       RISCV_FEATURE_PMP,
>       RISCV_FEATURE_EPMP,
> -    RISCV_FEATURE_DEBUG
>   };
>   
>   /* Privileged specification version */
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index ad8d82662c..4cdd247c6c 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
>           flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
>                              get_field(env->mstatus_hs, MSTATUS_VS));
>       }
> -    if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
> +    if (cpu->cfg.debug && !icount_enabled()) {
>           flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
>       }
>   #endif
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 4f9cc501b2..af4a44b33b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
>   
>   static RISCVException debug(CPURISCVState *env, int csrno)
>   {
> -    if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
> +    if (riscv_cpu_cfg(env).debug) {
>           return RISCV_EXCP_NONE;
>       }
>   
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index c6ce318cce..4634968898 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = {
>   static bool debug_needed(void *opaque)
>   {
>       RISCVCPU *cpu = opaque;
> -    CPURISCVState *env = &cpu->env;
>   
> -    return riscv_feature(env, RISCV_FEATURE_DEBUG);
> +    return cpu->cfg.debug;
>   }
>   
>   static int debug_post_load(void *opaque, int version_id)

[PATCH 06/11] target/riscv/cpu.c: error out if EPMP is enabled without PMP

[Daniel Henrique Barboza]

Instead of silently ignoring the EPMP setting if there is no PMP
available, error out informing the user that EPMP depends on PMP
support:

$ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true
qemu-system-riscv64: Invalid configuration: EPMP requires PMP support

This will force users to pick saner options in the QEMU command line.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 272cf1a8bf..1e67e72f90 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -925,13 +925,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
 
     if (cpu->cfg.pmp) {
         riscv_set_feature(env, RISCV_FEATURE_PMP);
+    }
+
+    if (cpu->cfg.epmp) {
+        riscv_set_feature(env, RISCV_FEATURE_EPMP);
 
         /*
          * Enhanced PMP should only be available
          * on harts with PMP support
          */
-        if (cpu->cfg.epmp) {
-            riscv_set_feature(env, RISCV_FEATURE_EPMP);
+        if (!cpu->cfg.pmp) {
+            error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+            return;
         }
     }
 
-- 
2.39.1

Re: [PATCH 06/11] target/riscv/cpu.c: error out if EPMP is enabled without PMP

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> Instead of silently ignoring the EPMP setting if there is no PMP
> available, error out informing the user that EPMP depends on PMP
> support:
>
> $ ./qemu-system-riscv64 -cpu rv64,pmp=false,x-epmp=true
> qemu-system-riscv64: Invalid configuration: EPMP requires PMP support
>
> This will force users to pick saner options in the QEMU command line.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.c | 9 +++++++--
>   1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 272cf1a8bf..1e67e72f90 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -925,13 +925,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>   
>       if (cpu->cfg.pmp) {
>           riscv_set_feature(env, RISCV_FEATURE_PMP);
> +    }
> +
> +    if (cpu->cfg.epmp) {
> +        riscv_set_feature(env, RISCV_FEATURE_EPMP);
>   
>           /*
>            * Enhanced PMP should only be available
>            * on harts with PMP support
>            */
> -        if (cpu->cfg.epmp) {
> -            riscv_set_feature(env, RISCV_FEATURE_EPMP);
> +        if (!cpu->cfg.pmp) {
> +            error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> +            return;
>           }
>       }
>   

[PATCH 07/11] target/riscv: remove RISCV_FEATURE_EPMP

[Daniel Henrique Barboza]

RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
flag. Use the flag directly.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c | 10 +++-------
 target/riscv/cpu.h |  1 -
 target/riscv/csr.c |  2 +-
 target/riscv/pmp.c |  4 ++--
 4 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e67e72f90..430b6adccb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         riscv_set_feature(env, RISCV_FEATURE_PMP);
     }
 
-    if (cpu->cfg.epmp) {
-        riscv_set_feature(env, RISCV_FEATURE_EPMP);
-
+    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
         /*
          * Enhanced PMP should only be available
          * on harts with PMP support
          */
-        if (!cpu->cfg.pmp) {
-            error_setg(errp, "Invalid configuration: EPMP requires PMP support");
-            return;
-        }
+        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
+        return;
     }
 
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 46de6f2f7f..d0de11fd41 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -88,7 +88,6 @@
 enum {
     RISCV_FEATURE_MMU,
     RISCV_FEATURE_PMP,
-    RISCV_FEATURE_EPMP,
 };
 
 /* Privileged specification version */
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index af4a44b33b..5b974dad6b 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
 
 static RISCVException epmp(CPURISCVState *env, int csrno)
 {
-    if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
+    if (env->priv == PRV_M && riscv_cpu_cfg(env).epmp) {
         return RISCV_EXCP_NONE;
     }
 
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 4bc4113531..bb54899635 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
     if (pmp_index < MAX_RISCV_PMPS) {
         bool locked = true;
 
-        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+        if (riscv_cpu_cfg(env).epmp) {
             /* mseccfg.RLB is set */
             if (MSECCFG_RLB_ISSET(env)) {
                 locked = false;
@@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
 {
     bool ret;
 
-    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+    if (riscv_cpu_cfg(env).epmp) {
         if (MSECCFG_MMWP_ISSET(env)) {
             /*
              * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
-- 
2.39.1

Re: [PATCH 07/11] target/riscv: remove RISCV_FEATURE_EPMP

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp
> flag. Use the flag directly.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.c | 10 +++-------
>   target/riscv/cpu.h |  1 -
>   target/riscv/csr.c |  2 +-
>   target/riscv/pmp.c |  4 ++--
>   4 files changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1e67e72f90..430b6adccb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -927,17 +927,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>           riscv_set_feature(env, RISCV_FEATURE_PMP);
>       }
>   
> -    if (cpu->cfg.epmp) {
> -        riscv_set_feature(env, RISCV_FEATURE_EPMP);
> -
> +    if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>           /*
>            * Enhanced PMP should only be available
>            * on harts with PMP support
>            */
> -        if (!cpu->cfg.pmp) {
> -            error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> -            return;
> -        }
> +        error_setg(errp, "Invalid configuration: EPMP requires PMP support");
> +        return;
>       }
>   
>   
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 46de6f2f7f..d0de11fd41 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -88,7 +88,6 @@
>   enum {
>       RISCV_FEATURE_MMU,
>       RISCV_FEATURE_PMP,
> -    RISCV_FEATURE_EPMP,
>   };
>   
>   /* Privileged specification version */
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index af4a44b33b..5b974dad6b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -428,7 +428,7 @@ static RISCVException pmp(CPURISCVState *env, int csrno)
>   
>   static RISCVException epmp(CPURISCVState *env, int csrno)
>   {
> -    if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
> +    if (env->priv == PRV_M && riscv_cpu_cfg(env).epmp) {
>           return RISCV_EXCP_NONE;
>       }
>   
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 4bc4113531..bb54899635 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -88,7 +88,7 @@ static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val)
>       if (pmp_index < MAX_RISCV_PMPS) {
>           bool locked = true;
>   
> -        if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
> +        if (riscv_cpu_cfg(env).epmp) {
>               /* mseccfg.RLB is set */
>               if (MSECCFG_RLB_ISSET(env)) {
>                   locked = false;
> @@ -239,7 +239,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
>   {
>       bool ret;
>   
> -    if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
> +    if (riscv_cpu_cfg(env).epmp) {
>           if (MSECCFG_MMWP_ISSET(env)) {
>               /*
>                * The Machine Mode Whitelist Policy (mseccfg.MMWP) is set

[PATCH 08/11] target/riscv: remove RISCV_FEATURE_PMP

[Daniel Henrique Barboza]

RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
cpu->cfg.pmp flag. Use the flag instead.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c        | 4 ----
 target/riscv/cpu.h        | 1 -
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 2 +-
 target/riscv/machine.c    | 3 +--
 target/riscv/op_helper.c  | 2 +-
 target/riscv/pmp.c        | 2 +-
 7 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 430b6adccb..a803395ed1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         riscv_set_feature(env, RISCV_FEATURE_MMU);
     }
 
-    if (cpu->cfg.pmp) {
-        riscv_set_feature(env, RISCV_FEATURE_PMP);
-    }
-
     if (cpu->cfg.epmp && !cpu->cfg.pmp) {
         /*
          * Enhanced PMP should only be available
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index d0de11fd41..62919cd5cc 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -87,7 +87,6 @@
    so a cpu features bitfield is required, likewise for optional PMP support */
 enum {
     RISCV_FEATURE_MMU,
-    RISCV_FEATURE_PMP,
 };
 
 /* Privileged specification version */
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4cdd247c6c..15d9542691 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
     pmp_priv_t pmp_priv;
     int pmp_index = -1;
 
-    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
+    if (!riscv_cpu_cfg(env).pmp) {
         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         return TRANSLATE_SUCCESS;
     }
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5b974dad6b..3d55b1b138 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
 
 static RISCVException pmp(CPURISCVState *env, int csrno)
 {
-    if (riscv_feature(env, RISCV_FEATURE_PMP)) {
+    if (riscv_cpu_cfg(env).pmp) {
         return RISCV_EXCP_NONE;
     }
 
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 4634968898..67e9e56853 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -27,9 +27,8 @@
 static bool pmp_needed(void *opaque)
 {
     RISCVCPU *cpu = opaque;
-    CPURISCVState *env = &cpu->env;
 
-    return riscv_feature(env, RISCV_FEATURE_PMP);
+    return cpu->cfg.pmp;
 }
 
 static int pmp_post_load(void *opaque, int version_id)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 48f918b71b..f34701b443 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env)
     uint64_t mstatus = env->mstatus;
     target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
 
-    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
+    if (riscv_cpu_cfg(env).pmp &&
         !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
         riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
     }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index bb54899635..1e7903dffa 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
         }
     }
 
-    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+    if (!riscv_cpu_cfg(env).pmp || (mode == PRV_M)) {
         /*
          * Privileged spec v1.10 states if HW doesn't implement any PMP entry
          * or no PMP entry matches an M-Mode access, the access succeeds.
-- 
2.39.1

Re: [PATCH 08/11] target/riscv: remove RISCV_FEATURE_PMP

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the
> cpu->cfg.pmp flag. Use the flag instead.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

> ---
>   target/riscv/cpu.c        | 4 ----
>   target/riscv/cpu.h        | 1 -
>   target/riscv/cpu_helper.c | 2 +-
>   target/riscv/csr.c        | 2 +-
>   target/riscv/machine.c    | 3 +--
>   target/riscv/op_helper.c  | 2 +-
>   target/riscv/pmp.c        | 2 +-
>   7 files changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 430b6adccb..a803395ed1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -923,10 +923,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>           riscv_set_feature(env, RISCV_FEATURE_MMU);
>       }
>   
> -    if (cpu->cfg.pmp) {
> -        riscv_set_feature(env, RISCV_FEATURE_PMP);
> -    }
> -
>       if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>           /*
>            * Enhanced PMP should only be available
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index d0de11fd41..62919cd5cc 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -87,7 +87,6 @@
>      so a cpu features bitfield is required, likewise for optional PMP support */
>   enum {
>       RISCV_FEATURE_MMU,
> -    RISCV_FEATURE_PMP,
>   };
>   
>   /* Privileged specification version */
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4cdd247c6c..15d9542691 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -706,7 +706,7 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot,
>       pmp_priv_t pmp_priv;
>       int pmp_index = -1;
>   
> -    if (!riscv_feature(env, RISCV_FEATURE_PMP)) {
> +    if (!riscv_cpu_cfg(env).pmp) {
>           *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>           return TRANSLATE_SUCCESS;
>       }
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 5b974dad6b..3d55b1b138 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -419,7 +419,7 @@ static int aia_hmode32(CPURISCVState *env, int csrno)
>   
>   static RISCVException pmp(CPURISCVState *env, int csrno)
>   {
> -    if (riscv_feature(env, RISCV_FEATURE_PMP)) {
> +    if (riscv_cpu_cfg(env).pmp) {
>           return RISCV_EXCP_NONE;
>       }
>   
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 4634968898..67e9e56853 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -27,9 +27,8 @@
>   static bool pmp_needed(void *opaque)
>   {
>       RISCVCPU *cpu = opaque;
> -    CPURISCVState *env = &cpu->env;
>   
> -    return riscv_feature(env, RISCV_FEATURE_PMP);
> +    return cpu->cfg.pmp;
>   }
>   
>   static int pmp_post_load(void *opaque, int version_id)
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 48f918b71b..f34701b443 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -195,7 +195,7 @@ target_ulong helper_mret(CPURISCVState *env)
>       uint64_t mstatus = env->mstatus;
>       target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);
>   
> -    if (riscv_feature(env, RISCV_FEATURE_PMP) &&
> +    if (riscv_cpu_cfg(env).pmp &&
>           !pmp_get_num_rules(env) && (prev_priv != PRV_M)) {
>           riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC());
>       }
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index bb54899635..1e7903dffa 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -265,7 +265,7 @@ static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong addr,
>           }
>       }
>   
> -    if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
> +    if (!riscv_cpu_cfg(env).pmp || (mode == PRV_M)) {
>           /*
>            * Privileged spec v1.10 states if HW doesn't implement any PMP entry
>            * or no PMP entry matches an M-Mode access, the access succeeds.

[PATCH 09/11] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()

[Daniel Henrique Barboza]

Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
riscv_isa_string().

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 hw/riscv/virt.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..8ab6a3ec16 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
     bool is_32_bit = riscv_is_32bit(&s->soc[0]);
 
     for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
+        RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
+        RISCVCPUConfig cpu_cfg = cpu_ptr->cfg;
         cpu_phandle = (*phandle)++;
 
         cpu_name = g_strdup_printf("/cpus/cpu@%d",
             s->soc[socket].hartid_base + cpu);
         qemu_fdt_add_subnode(ms->fdt, cpu_name);
-        if (riscv_feature(&s->soc[socket].harts[cpu].env,
-                          RISCV_FEATURE_MMU)) {
+        if (cpu_cfg.mmu) {
             qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                     (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
         } else {
             qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
                                     "riscv,none");
         }
-        name = riscv_isa_string(&s->soc[socket].harts[cpu]);
+        name = riscv_isa_string(cpu_ptr);
         qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
         g_free(name);
         qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");
-- 
2.39.1

Re: [PATCH 09/11] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> Read cpu_ptr->cfg.mmu directly. As a bonus, use cpu_ptr in
> riscv_isa_string().
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   hw/riscv/virt.c | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 86c4adc0c9..8ab6a3ec16 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -232,20 +232,21 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket,
>       bool is_32_bit = riscv_is_32bit(&s->soc[0]);
>   
>       for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) {
> +        RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu];
> +        RISCVCPUConfig cpu_cfg = cpu_ptr->cfg;

Adding cpu_cfg seems not very necessary.

Otherwise, Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li

>           cpu_phandle = (*phandle)++;
>   
>           cpu_name = g_strdup_printf("/cpus/cpu@%d",
>               s->soc[socket].hartid_base + cpu);
>           qemu_fdt_add_subnode(ms->fdt, cpu_name);
> -        if (riscv_feature(&s->soc[socket].harts[cpu].env,
> -                          RISCV_FEATURE_MMU)) {
> +        if (cpu_cfg.mmu) {
>               qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
>                                       (is_32_bit) ? "riscv,sv32" : "riscv,sv48");
>           } else {
>               qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
>                                       "riscv,none");
>           }
> -        name = riscv_isa_string(&s->soc[socket].harts[cpu]);
> +        name = riscv_isa_string(cpu_ptr);
>           qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name);
>           g_free(name);
>           qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv");

[PATCH 10/11] target/riscv: remove RISCV_FEATURE_MMU

[Daniel Henrique Barboza]

RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use
the flag directly instead.

With this change the enum is also removed. It is worth noticing that
this enum, and all the RISCV_FEATURES_* that were contained in it,
predates the existence of the cpu->cfg object. Today, using cpu->cfg is
an easier way to retrieve all the features and extensions enabled in the
hart.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.c        | 4 ----
 target/riscv/cpu.h        | 7 -------
 target/riscv/cpu_helper.c | 2 +-
 target/riscv/csr.c        | 4 ++--
 target/riscv/monitor.c    | 2 +-
 target/riscv/pmp.c        | 2 +-
 6 files changed, 5 insertions(+), 16 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a803395ed1..2859ebc3e6 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
         }
     }
 
-    if (cpu->cfg.mmu) {
-        riscv_set_feature(env, RISCV_FEATURE_MMU);
-    }
-
     if (cpu->cfg.epmp && !cpu->cfg.pmp) {
         /*
          * Enhanced PMP should only be available
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 62919cd5cc..83a9fa38d9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,13 +81,6 @@
 #define RVH RV('H')
 #define RVJ RV('J')
 
-/* S extension denotes that Supervisor mode exists, however it is possible
-   to have a core that support S mode but does not have an MMU and there
-   is currently no bit in misa to indicate whether an MMU exists or not
-   so a cpu features bitfield is required, likewise for optional PMP support */
-enum {
-    RISCV_FEATURE_MMU,
-};
 
 /* Privileged specification version */
 enum {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 15d9542691..e76b206191 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
         mode = PRV_U;
     }
 
-    if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
+    if (mode == PRV_M || !riscv_cpu_cfg(env).mmu) {
         *physical = addr;
         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
         return TRANSLATE_SUCCESS;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 3d55b1b138..9fb8e86b70 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2623,7 +2623,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno,
 static RISCVException read_satp(CPURISCVState *env, int csrno,
                                 target_ulong *val)
 {
-    if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+    if (!riscv_cpu_cfg(env).mmu) {
         *val = 0;
         return RISCV_EXCP_NONE;
     }
@@ -2642,7 +2642,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
 {
     target_ulong vm, mask;
 
-    if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+    if (!riscv_cpu_cfg(env).mmu) {
         return RISCV_EXCP_NONE;
     }
 
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 236f93b9f5..b7b8d0614f 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
         return;
     }
 
-    if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+    if (!riscv_cpu_cfg(env).mmu) {
         monitor_printf(mon, "S-mode MMU unavailable\n");
         return;
     }
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index 1e7903dffa..c67de36942 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
     }
 
     if (size == 0) {
-        if (riscv_feature(env, RISCV_FEATURE_MMU)) {
+        if (riscv_cpu_cfg(env).mmu) {
             /*
              * If size is unknown (0), assume that all bytes
              * from addr to the end of the page will be accessed.
-- 
2.39.1

Re: [PATCH 10/11] target/riscv: remove RISCV_FEATURE_MMU

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> RISCV_FEATURE_MMU is set whether cpu->cfg.mmu is set, so let's just use
> the flag directly instead.
>
> With this change the enum is also removed. It is worth noticing that
> this enum, and all the RISCV_FEATURES_* that were contained in it,
> predates the existence of the cpu->cfg object. Today, using cpu->cfg is
> an easier way to retrieve all the features and extensions enabled in the
> hart.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li
> ---
>   target/riscv/cpu.c        | 4 ----
>   target/riscv/cpu.h        | 7 -------
>   target/riscv/cpu_helper.c | 2 +-
>   target/riscv/csr.c        | 4 ++--
>   target/riscv/monitor.c    | 2 +-
>   target/riscv/pmp.c        | 2 +-
>   6 files changed, 5 insertions(+), 16 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a803395ed1..2859ebc3e6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -919,10 +919,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>           }
>       }
>   
> -    if (cpu->cfg.mmu) {
> -        riscv_set_feature(env, RISCV_FEATURE_MMU);
> -    }
> -
>       if (cpu->cfg.epmp && !cpu->cfg.pmp) {
>           /*
>            * Enhanced PMP should only be available
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 62919cd5cc..83a9fa38d9 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -81,13 +81,6 @@
>   #define RVH RV('H')
>   #define RVJ RV('J')
>   
> -/* S extension denotes that Supervisor mode exists, however it is possible
> -   to have a core that support S mode but does not have an MMU and there
> -   is currently no bit in misa to indicate whether an MMU exists or not
> -   so a cpu features bitfield is required, likewise for optional PMP support */
> -enum {
> -    RISCV_FEATURE_MMU,
> -};
>   
>   /* Privileged specification version */
>   enum {
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 15d9542691..e76b206191 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -796,7 +796,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
>           mode = PRV_U;
>       }
>   
> -    if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) {
> +    if (mode == PRV_M || !riscv_cpu_cfg(env).mmu) {
>           *physical = addr;
>           *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
>           return TRANSLATE_SUCCESS;
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 3d55b1b138..9fb8e86b70 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -2623,7 +2623,7 @@ static RISCVException rmw_siph(CPURISCVState *env, int csrno,
>   static RISCVException read_satp(CPURISCVState *env, int csrno,
>                                   target_ulong *val)
>   {
> -    if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> +    if (!riscv_cpu_cfg(env).mmu) {
>           *val = 0;
>           return RISCV_EXCP_NONE;
>       }
> @@ -2642,7 +2642,7 @@ static RISCVException write_satp(CPURISCVState *env, int csrno,
>   {
>       target_ulong vm, mask;
>   
> -    if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> +    if (!riscv_cpu_cfg(env).mmu) {
>           return RISCV_EXCP_NONE;
>       }
>   
> diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
> index 236f93b9f5..b7b8d0614f 100644
> --- a/target/riscv/monitor.c
> +++ b/target/riscv/monitor.c
> @@ -218,7 +218,7 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
>           return;
>       }
>   
> -    if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
> +    if (!riscv_cpu_cfg(env).mmu) {
>           monitor_printf(mon, "S-mode MMU unavailable\n");
>           return;
>       }
> diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
> index 1e7903dffa..c67de36942 100644
> --- a/target/riscv/pmp.c
> +++ b/target/riscv/pmp.c
> @@ -315,7 +315,7 @@ int pmp_hart_has_privs(CPURISCVState *env, target_ulong addr,
>       }
>   
>       if (size == 0) {
> -        if (riscv_feature(env, RISCV_FEATURE_MMU)) {
> +        if (riscv_cpu_cfg(env).mmu) {
>               /*
>                * If size is unknown (0), assume that all bytes
>                * from addr to the end of the page will be accessed.

[PATCH 11/11] target/riscv/cpu: remove CPUArchState::features and friends

[Daniel Henrique Barboza]

The attribute is no longer used since we can retrieve all the enabled
features in the hart by using cpu->cfg instead.

Remove env->feature, riscv_feature() and riscv_set_feature(). We also
need to bump vmstate_riscv_cpu version_id and minimal_version_id since
'features' is no longer being migrated.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
 target/riscv/cpu.h     | 12 ------------
 target/riscv/machine.c |  5 ++---
 2 files changed, 2 insertions(+), 15 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 83a9fa38d9..6290c6d357 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -173,8 +173,6 @@ struct CPUArchState {
     /* 128-bit helpers upper part return value */
     target_ulong retxh;
 
-    uint32_t features;
-
 #ifdef CONFIG_USER_ONLY
     uint32_t elf_flags;
 #endif
@@ -525,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
     return (env->misa_ext & ext) != 0;
 }
 
-static inline bool riscv_feature(CPURISCVState *env, int feature)
-{
-    return env->features & (1ULL << feature);
-}
-
-static inline void riscv_set_feature(CPURISCVState *env, int feature)
-{
-    env->features |= (1ULL << feature);
-}
-
 #include "cpu_user.h"
 
 extern const char * const riscv_int_regnames[];
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 67e9e56853..9c455931d8 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
 
 const VMStateDescription vmstate_riscv_cpu = {
     .name = "cpu",
-    .version_id = 6,
-    .minimum_version_id = 6,
+    .version_id = 7,
+    .minimum_version_id = 7,
     .post_load = riscv_cpu_post_load,
     .fields = (VMStateField[]) {
         VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
@@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = {
         VMSTATE_UINT32(env.misa_ext, RISCVCPU),
         VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
         VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
-        VMSTATE_UINT32(env.features, RISCVCPU),
         VMSTATE_UINTTL(env.priv, RISCVCPU),
         VMSTATE_UINTTL(env.virt, RISCVCPU),
         VMSTATE_UINT64(env.resetvec, RISCVCPU),
-- 
2.39.1

Re: [PATCH 11/11] target/riscv/cpu: remove CPUArchState^features and friends

[weiwei]

On 2023/2/10 21:36, Daniel Henrique Barboza wrote:
> The attribute is no longer used since we can retrieve all the enabled
> features in the hart by using cpu->cfg instead.
>
> Remove env->feature, riscv_feature() and riscv_set_feature(). We also
> need to bump vmstate_riscv_cpu version_id and minimal_version_id since
> 'features' is no longer being migrated.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>

Regards,

Weiwei Li
> ---
>   target/riscv/cpu.h     | 12 ------------
>   target/riscv/machine.c |  5 ++---
>   2 files changed, 2 insertions(+), 15 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 83a9fa38d9..6290c6d357 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -173,8 +173,6 @@ struct CPUArchState {
>       /* 128-bit helpers upper part return value */
>       target_ulong retxh;
>   
> -    uint32_t features;
> -
>   #ifdef CONFIG_USER_ONLY
>       uint32_t elf_flags;
>   #endif
> @@ -525,16 +523,6 @@ static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
>       return (env->misa_ext & ext) != 0;
>   }
>   
> -static inline bool riscv_feature(CPURISCVState *env, int feature)
> -{
> -    return env->features & (1ULL << feature);
> -}
> -
> -static inline void riscv_set_feature(CPURISCVState *env, int feature)
> -{
> -    env->features |= (1ULL << feature);
> -}
> -
>   #include "cpu_user.h"
>   
>   extern const char * const riscv_int_regnames[];
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 67e9e56853..9c455931d8 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -331,8 +331,8 @@ static const VMStateDescription vmstate_pmu_ctr_state = {
>   
>   const VMStateDescription vmstate_riscv_cpu = {
>       .name = "cpu",
> -    .version_id = 6,
> -    .minimum_version_id = 6,
> +    .version_id = 7,
> +    .minimum_version_id = 7,
>       .post_load = riscv_cpu_post_load,
>       .fields = (VMStateField[]) {
>           VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -351,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu = {
>           VMSTATE_UINT32(env.misa_ext, RISCVCPU),
>           VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
>           VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
> -        VMSTATE_UINT32(env.features, RISCVCPU),
>           VMSTATE_UINTTL(env.priv, RISCVCPU),
>           VMSTATE_UINTTL(env.virt, RISCVCPU),
>           VMSTATE_UINT64(env.resetvec, RISCVCPU),