From: "Michael S. Tsirkin" <mst@redhat.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Li Zhijian <lizhijian@fujitsu.com>,
Jonathan Cameron <jonathan.cameron@huawei.com>,
Fan Ni <fan.ni@samsung.com>
Subject: [PULL 46/48] hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
Date: Wed, 15 Jan 2025 13:10:55 -0500 [thread overview]
Message-ID: <1ce979e7269a34d19ea1a65808df014d8b2acbf6.1736964488.git.mst@redhat.com> (raw)
In-Reply-To: <cover.1736964487.git.mst@redhat.com>
From: Li Zhijian <lizhijian@fujitsu.com>
This assertion always happens when we sanitize the CXL memory device.
$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
It is incorrect to register an MSIX number beyond the device's capability.
Increase the device's MSIX number to cover the mailbox msix number(9).
Fixes: 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background completion")
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Message-Id: <20250115075834.167504-1-lizhijian@fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/mem/cxl_type3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index bd7652740f..0ae1704a34 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -843,7 +843,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
ComponentRegisters *regs = &cxl_cstate->crb;
MemoryRegion *mr = ®s->component_registers;
uint8_t *pci_conf = pci_dev->config;
- unsigned short msix_num = 6;
+ unsigned short msix_num = 10;
int i, rc;
uint16_t count;
--
MST
next prev parent reply other threads:[~2025-01-15 18:17 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-15 18:08 [PULL 00/48] virtio,pc,pci: features, fixes, cleanups Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 01/48] virtio-gpu: Add definition for resource_uuid feature Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 02/48] pci: ensure valid link status bits for downstream ports Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 03/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 04/48] cpuhp: make sure that remove events are handled within the same SCI Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 05/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 06/48] intel_iommu: Use the latest fault reasons defined by spec Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 07/48] intel_iommu: Make pasid entry type check accurate Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 08/48] intel_iommu: Add a placeholder variable for scalable mode stage-1 translation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 09/48] intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation Michael S. Tsirkin
2025-01-15 18:08 ` [PULL 10/48] intel_iommu: Rename slpte to pte Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 11/48] intel_iommu: Implement stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 12/48] intel_iommu: Check if the input address is canonical Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 13/48] intel_iommu: Check stage-1 translation result with interrupt range Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 14/48] intel_iommu: Set accessed and dirty bits during stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 15/48] intel_iommu: Flush stage-1 cache in iotlb invalidation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 16/48] intel_iommu: Process PASID-based " Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 17/48] intel_iommu: Add an internal API to find an address space with PASID Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 18/48] intel_iommu: Add support for PASID-based device IOTLB invalidation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 19/48] intel_iommu: piotlb invalidation should notify unmap Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 20/48] tests/acpi: q35: allow DMAR acpi table changes Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 21/48] intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2 Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 22/48] tests/acpi: q35: Update host address width in DMAR Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 23/48] intel_iommu: Introduce a property x-flts for stage-1 translation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 24/48] intel_iommu: Introduce a property to control FS1GP cap bit setting Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 25/48] tests/qtest: Add intel-iommu test Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 26/48] pci/msix: Fix msix pba read vector poll end calculation Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 27/48] acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 28/48] acpi/ghes: simplify acpi_ghes_record_errors() code Michael S. Tsirkin
2025-01-15 18:09 ` [PULL 29/48] acpi/ghes: simplify the per-arch caller to build HEST table Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 30/48] acpi/ghes: better handle source_id and notification Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 31/48] acpi/ghes: Fix acpi_ghes_record_errors() argument Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 32/48] acpi/ghes: Remove a duplicated out of bounds check Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 33/48] acpi/ghes: Change the type for source_id Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 34/48] acpi/ghes: don't check if physical_address is not zero Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 35/48] acpi/ghes: make the GHES record generation more generic Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 36/48] acpi/ghes: better name GHES memory error function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 37/48] acpi/ghes: don't crash QEMU if ghes GED is not found Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 38/48] acpi/ghes: rename etc/hardware_error file macros Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 39/48] acpi/ghes: better name the offset of the hardware error firmware Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 40/48] acpi/ghes: move offset calculus to a separate function Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 41/48] acpi/ghes: Change ghes fill logic to work with only one source Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 42/48] docs: acpi_hest_ghes: fix documentation for CPER size Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 43/48] tests: acpi: whitelist expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 44/48] pci: acpi: Windows 'PCI Label Id' bug workaround Michael S. Tsirkin
2025-01-15 18:10 ` [PULL 45/48] tests: acpi: update expected blobs Michael S. Tsirkin
2025-01-15 18:10 ` Michael S. Tsirkin [this message]
2025-01-15 18:10 ` [PULL 47/48] vhost: Add stubs for the migration state transfer interface Michael S. Tsirkin
2025-01-15 18:11 ` [PULL 48/48] virtio-net: vhost-user: Implement internal migration Michael S. Tsirkin
2025-01-15 18:15 ` [PULL 00/48] virtio,pc,pci: features, fixes, cleanups David Woodhouse
2025-01-15 22:42 ` Michael S. Tsirkin
2025-01-15 23:05 ` David Woodhouse
2025-01-16 7:05 ` Michael S. Tsirkin
2025-01-16 14:06 ` David Woodhouse
2025-01-16 7:06 ` Michael S. Tsirkin
2025-01-16 22:10 ` Stefan Hajnoczi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1ce979e7269a34d19ea1a65808df014d8b2acbf6.1736964488.git.mst@redhat.com \
--to=mst@redhat.com \
--cc=fan.ni@samsung.com \
--cc=jonathan.cameron@huawei.com \
--cc=lizhijian@fujitsu.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).