From: CLEMENT MATHIEU--DRIF <clement.mathieu--drif@eviden.com>
To: Zhenzhong Duan <zhenzhong.duan@intel.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "alex.williamson@redhat.com" <alex.williamson@redhat.com>,
"clg@redhat.com" <clg@redhat.com>,
"eric.auger@redhat.com" <eric.auger@redhat.com>,
"mst@redhat.com" <mst@redhat.com>,
"jasowang@redhat.com" <jasowang@redhat.com>,
"peterx@redhat.com" <peterx@redhat.com>,
"ddutile@redhat.com" <ddutile@redhat.com>,
"jgg@nvidia.com" <jgg@nvidia.com>,
"nicolinc@nvidia.com" <nicolinc@nvidia.com>,
"shameerali.kolothum.thodi@huawei.com"
<shameerali.kolothum.thodi@huawei.com>,
"joao.m.martins@oracle.com" <joao.m.martins@oracle.com>,
"kevin.tian@intel.com" <kevin.tian@intel.com>,
"yi.l.liu@intel.com" <yi.l.liu@intel.com>,
"chao.p.peng@intel.com" <chao.p.peng@intel.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH v1 04/15] intel_iommu: Introduce a new structure VTDHostIOMMUDevice
Date: Thu, 12 Jun 2025 16:04:46 +0000 [thread overview]
Message-ID: <1cf2ecbe-1f98-452f-8a39-331e7d459969@eviden.com> (raw)
In-Reply-To: <20250606100416.346132-5-zhenzhong.duan@intel.com>
Hi,
On 06/06/2025 12:04 pm, Zhenzhong Duan wrote:
> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
>
>
> Introduce a new structure VTDHostIOMMUDevice which replaces
> HostIOMMUDevice to be stored in hash table.
>
> It includes a reference to HostIOMMUDevice and IntelIOMMUState,
> also includes BDF information which will be used in future
> patches.
>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
> hw/i386/intel_iommu_internal.h | 7 +++++++
> include/hw/i386/intel_iommu.h | 2 +-
> hw/i386/intel_iommu.c | 14 ++++++++++++--
> 3 files changed, 20 insertions(+), 3 deletions(-)
>
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 2cda744786..18bc22fc72 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -28,6 +28,7 @@
> #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H
> #define HW_I386_INTEL_IOMMU_INTERNAL_H
> #include "hw/i386/intel_iommu.h"
> +#include "system/host_iommu_device.h"
>
> /*
> * Intel IOMMU register specification
> @@ -608,4 +609,10 @@ typedef struct VTDRootEntry VTDRootEntry;
> /* Bits to decide the offset for each level */
> #define VTD_LEVEL_BITS 9
>
> +typedef struct VTDHostIOMMUDevice {
> + IntelIOMMUState *iommu_state;
> + PCIBus *bus;
> + uint8_t devfn;
> + HostIOMMUDevice *hiod;
> +} VTDHostIOMMUDevice;
> #endif
> diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
> index e95477e855..50f9b27a45 100644
> --- a/include/hw/i386/intel_iommu.h
> +++ b/include/hw/i386/intel_iommu.h
> @@ -295,7 +295,7 @@ struct IntelIOMMUState {
> /* list of registered notifiers */
> QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers;
>
> - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */
> + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */
>
> /* interrupt remapping */
> bool intr_enabled; /* Whether guest enabled IR */
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index c42ef83ddc..796b71605c 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -281,7 +281,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gconstpointer v2)
>
> static void vtd_hiod_destroy(gpointer v)
> {
> - object_unref(v);
> + VTDHostIOMMUDevice *vtd_hiod = v;
> +
> + object_unref(vtd_hiod->hiod);
> + g_free(vtd_hiod);
> }
>
> static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
> @@ -4397,6 +4400,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
> HostIOMMUDevice *hiod, Error **errp)
> {
> IntelIOMMUState *s = opaque;
> + VTDHostIOMMUDevice *vtd_hiod;
> struct vtd_as_key key = {
> .bus = bus,
> .devfn = devfn,
> @@ -4413,6 +4417,12 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
> return false;
> }
>
> + vtd_hiod = g_malloc0(sizeof(VTDHostIOMMUDevice));
> + vtd_hiod->bus = bus;
> + vtd_hiod->devfn = (uint8_t)devfn;
> + vtd_hiod->iommu_state = s;
> + vtd_hiod->hiod = hiod;
> +
> if (!vtd_check_hiod(s, hiod, errp)) {
Shouldn't we free vtd_hiod here?
> vtd_iommu_unlock(s);
> return false;
> @@ -4423,7 +4433,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn,
> new_key->devfn = devfn;
>
> object_ref(hiod);
> - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod);
> + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod);
>
> vtd_iommu_unlock(s);
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-06-12 16:05 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-06 10:04 [PATCH v1 00/15] intel_iommu: Enable stage-1 translation for passthrough device Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 01/15] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Zhenzhong Duan
2025-06-11 7:20 ` Yi Liu
2025-06-17 17:16 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 02/15] intel_iommu: Optimize context entry cache utilization Zhenzhong Duan
2025-06-11 7:48 ` Yi Liu
2025-06-11 10:06 ` Duan, Zhenzhong
2025-06-17 10:57 ` Yi Liu
2025-06-18 1:58 ` Duan, Zhenzhong
2025-06-17 17:24 ` Eric Auger
2025-06-18 2:10 ` Duan, Zhenzhong
2025-06-18 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 03/15] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Zhenzhong Duan
2025-06-17 17:49 ` Eric Auger
2025-06-18 2:14 ` Duan, Zhenzhong
2025-06-18 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 04/15] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Zhenzhong Duan
2025-06-12 16:04 ` CLEMENT MATHIEU--DRIF [this message]
2025-06-13 9:08 ` Duan, Zhenzhong
2025-06-20 7:08 ` Eric Auger
2025-06-06 10:04 ` [PATCH v1 05/15] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Zhenzhong Duan
2025-06-11 9:54 ` Yi Liu
2025-06-11 10:46 ` Duan, Zhenzhong
2025-06-17 10:58 ` Yi Liu
2025-06-06 10:04 ` [PATCH v1 06/15] intel_iommu: Handle PASID entry removing and updating Zhenzhong Duan
2025-06-17 12:29 ` Yi Liu
2025-06-18 6:03 ` Duan, Zhenzhong
2025-06-06 10:04 ` [PATCH v1 07/15] intel_iommu: Handle PASID entry adding Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 08/15] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 09/15] intel_iommu: Bind/unbind guest page table to host Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 10/15] intel_iommu: ERRATA_772415 workaround Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 11/15] intel_iommu: Replay pasid binds after context cache invalidation Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 12/15] intel_iommu: Propagate PASID-based iotlb invalidation to host Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 13/15] intel_iommu: Refresh pasid bind when either SRTP or TE bit is changed Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 14/15] intel_iommu: Bypass replay in stage-1 page table mode Zhenzhong Duan
2025-06-06 10:04 ` [PATCH v1 15/15] intel_iommu: Enable host device when x-flts=on in scalable mode Zhenzhong Duan
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