From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Evgeny Iakovlev" <eiakovlev@linux.microsoft.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Gavin Shan" <gshan@redhat.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
qemu-arm@nongnu.org
Subject: Re: [PATCH v2 06/11] hw/char/pl011: Extract pl011_write_txdata() from pl011_write()
Date: Thu, 12 Oct 2023 16:25:14 +0200 [thread overview]
Message-ID: <1d47574e-cc05-a087-f674-0644430a4682@linaro.org> (raw)
In-Reply-To: <39fb2593-2184-560b-3d67-51f9203f078a@linaro.org>
On 12/10/23 15:07, Philippe Mathieu-Daudé wrote:
> On 14/7/23 08:58, Richard Henderson wrote:
>> On 7/10/23 18:50, Philippe Mathieu-Daudé wrote:
>>> +static void pl011_write_txdata(PL011State *s, const uint8_t *buf,
>>> int length)
>>> +{
>>> + /* ??? Check if transmitter is enabled. */
>>> +
>>> + /* XXX this blocks entire thread. Rewrite to use
>>> + * qemu_chr_fe_write and background I/O callbacks */
>>> + qemu_chr_fe_write_all(&s->chr, buf, 1);
>>
>> Not using length?
>
> This is a simple "code extract" patch. Length is used when
> we switch to FIFO in the last patch.
Hmm you are right it isn't used...
The UARTDR register is 16-bit wide. Only 8 bits are used for data.
No need for a 'length' param here.
next prev parent reply other threads:[~2023-10-12 14:26 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 17:50 [PATCH v2 00/11] hw/char/pl011: Implement TX (async) FIFO to avoid blocking the main loop Philippe Mathieu-Daudé
2023-07-10 17:50 ` [PATCH v2 01/11] hw/char/pl011: Restrict MemoryRegionOps implementation access sizes Philippe Mathieu-Daudé
2023-07-14 6:47 ` Richard Henderson
2023-07-10 17:50 ` [PATCH v2 02/11] hw/char/pl011: Display register name in trace events Philippe Mathieu-Daudé
2023-07-14 6:49 ` Richard Henderson
2023-07-10 17:50 ` [PATCH v2 03/11] hw/char/pl011: Remove duplicated PL011_INT_[RT]X definitions Philippe Mathieu-Daudé
2023-07-14 6:50 ` Richard Henderson
2023-07-10 17:50 ` [PATCH v2 04/11] hw/char/pl011: Replace magic values by register field definitions Philippe Mathieu-Daudé
2023-07-14 6:54 ` Richard Henderson
2023-07-10 17:50 ` [PATCH v2 05/11] hw/char/pl011: Split RX/TX path of pl011_reset_fifo() Philippe Mathieu-Daudé
2023-07-14 6:56 ` Richard Henderson
2023-07-10 17:50 ` [PATCH v2 06/11] hw/char/pl011: Extract pl011_write_txdata() from pl011_write() Philippe Mathieu-Daudé
2023-07-14 6:58 ` Richard Henderson
2023-10-12 13:07 ` Philippe Mathieu-Daudé
2023-10-12 14:25 ` Philippe Mathieu-Daudé [this message]
2023-07-10 17:50 ` [PATCH v2 07/11] hw/char/pl011: Extract pl011_read_rxdata() from pl011_read() Philippe Mathieu-Daudé
2023-07-14 7:00 ` Richard Henderson
2023-07-10 17:50 ` [PATCH v2 08/11] hw/char/pl011: Warn when using disabled transmitter Philippe Mathieu-Daudé
2023-07-14 7:01 ` Richard Henderson
2023-07-10 17:51 ` [PATCH v2 09/11] hw/char/pl011: Check if receiver is enabled Philippe Mathieu-Daudé
2023-07-14 7:03 ` Richard Henderson
2023-07-10 17:51 ` [PATCH v2 10/11] hw/char/pl011: Rename RX FIFO methods Philippe Mathieu-Daudé
2023-07-14 7:06 ` Richard Henderson
2023-07-10 17:51 ` [RFC PATCH v2 11/11] hw/char/pl011: Implement TX FIFO Philippe Mathieu-Daudé
2023-07-14 7:27 ` Richard Henderson
2023-10-13 14:05 ` Philippe Mathieu-Daudé
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