qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, "Cédric Le Goater" <clg@kaod.org>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>
Subject: Re: [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration
Date: Fri, 30 Jun 2023 16:36:17 -0300	[thread overview]
Message-ID: <1d6fed0b-1338-d359-89af-9a4e30e97589@gmail.com> (raw)
In-Reply-To: <20230625120317.13877-2-npiggin@gmail.com>



On 6/25/23 09:03, Nicholas Piggin wrote:
> POWER book4 (implementation-specific) SPRs are sometimes in their own
> functions, but in other cases are mixed with architected SPRs. Do some
> spring cleaning on these.
> 
> Reviewed-by: Cédric Le Goater <clg@kaod.org>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---

Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,


Daniel

>   target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++--------------
>   1 file changed, 55 insertions(+), 27 deletions(-)
> 
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index a97fb7fe10..21ff4861c3 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -5370,31 +5370,6 @@ static void register_book3s_ids_sprs(CPUPPCState *env)
>                    &spr_read_generic, SPR_NOACCESS,
>                    &spr_read_generic, NULL,
>                    0x00000000);
> -    spr_register_hv(env, SPR_HID0, "HID0",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
> -    spr_register_hv(env, SPR_TSCR, "TSCR",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic32,
> -                 0x00000000);
> -    spr_register_hv(env, SPR_HMER, "HMER",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_hmer,
> -                 0x00000000);
> -    spr_register_hv(env, SPR_HMEER, "HMEER",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
> -    spr_register_hv(env, SPR_TFMR, "TFMR",
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 SPR_NOACCESS, SPR_NOACCESS,
> -                 &spr_read_generic, &spr_write_generic,
> -                 0x00000000);
>       spr_register_hv(env, SPR_LPIDR, "LPIDR",
>                    SPR_NOACCESS, SPR_NOACCESS,
>                    SPR_NOACCESS, SPR_NOACCESS,
> @@ -5656,14 +5631,60 @@ static void register_power8_ic_sprs(CPUPPCState *env)
>   #endif
>   }
>   
> +/* SPRs specific to IBM POWER CPUs */
> +static void register_power_common_book4_sprs(CPUPPCState *env)
> +{
> +#if !defined(CONFIG_USER_ONLY)
> +    spr_register_hv(env, SPR_HID0, "HID0",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, &spr_write_generic,
> +                 0x00000000);
> +    spr_register_hv(env, SPR_TSCR, "TSCR",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, &spr_write_generic32,
> +                 0x00000000);
> +    spr_register_hv(env, SPR_HMER, "HMER",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, &spr_write_hmer,
> +                 0x00000000);
> +    spr_register_hv(env, SPR_HMEER, "HMEER",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, &spr_write_generic,
> +                 0x00000000);
> +    spr_register_hv(env, SPR_TFMR, "TFMR",
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 SPR_NOACCESS, SPR_NOACCESS,
> +                 &spr_read_generic, &spr_write_generic,
> +                 0x00000000);
> +#endif
> +}
> +
> +static void register_power9_book4_sprs(CPUPPCState *env)
> +{
> +    /* Add a number of P9 book4 registers */
> +    register_power_common_book4_sprs(env);
> +#if !defined(CONFIG_USER_ONLY)
> +    spr_register_kvm(env, SPR_WORT, "WORT",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_generic,
> +                     KVM_REG_PPC_WORT, 0);
> +#endif
> +}
> +
>   static void register_power8_book4_sprs(CPUPPCState *env)
>   {
>       /* Add a number of P8 book4 registers */
> +    register_power_common_book4_sprs(env);
>   #if !defined(CONFIG_USER_ONLY)
>       spr_register_kvm(env, SPR_ACOP, "ACOP",
>                        SPR_NOACCESS, SPR_NOACCESS,
>                        &spr_read_generic, &spr_write_generic,
>                        KVM_REG_PPC_ACOP, 0);
> +    /* PID is only in BookE in ISA v2.07 */
>       spr_register_kvm(env, SPR_BOOKS_PID, "PID",
>                        SPR_NOACCESS, SPR_NOACCESS,
>                        &spr_read_generic, &spr_write_pidr,
> @@ -5679,10 +5700,12 @@ static void register_power7_book4_sprs(CPUPPCState *env)
>   {
>       /* Add a number of P7 book4 registers */
>   #if !defined(CONFIG_USER_ONLY)
> +    register_power_common_book4_sprs(env);
>       spr_register_kvm(env, SPR_ACOP, "ACOP",
>                        SPR_NOACCESS, SPR_NOACCESS,
>                        &spr_read_generic, &spr_write_generic,
>                        KVM_REG_PPC_ACOP, 0);
> +    /* PID is only in BookE in ISA v2.06 */
>       spr_register_kvm(env, SPR_BOOKS_PID, "PID",
>                        SPR_NOACCESS, SPR_NOACCESS,
>                        &spr_read_generic, &spr_write_generic32,
> @@ -5716,6 +5739,11 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
>                       SPR_NOACCESS, SPR_NOACCESS,
>                       &spr_read_generic, &spr_write_generic,
>                       0x0000000000000000);
> +    /* PID is part of the BookS ISA from v3.0 */
> +    spr_register_kvm(env, SPR_BOOKS_PID, "PID",
> +                     SPR_NOACCESS, SPR_NOACCESS,
> +                     &spr_read_generic, &spr_write_pidr,
> +                     KVM_REG_PPC_PID, 0);
>   #endif
>   }
>   
> @@ -6269,7 +6297,7 @@ static void init_proc_POWER9(CPUPPCState *env)
>       register_power8_dpdes_sprs(env);
>       register_vtb_sprs(env);
>       register_power8_ic_sprs(env);
> -    register_power8_book4_sprs(env);
> +    register_power9_book4_sprs(env);
>       register_power8_rpr_sprs(env);
>       register_power9_mmu_sprs(env);
>   
> @@ -6462,7 +6490,7 @@ static void init_proc_POWER10(CPUPPCState *env)
>       register_power8_dpdes_sprs(env);
>       register_vtb_sprs(env);
>       register_power8_ic_sprs(env);
> -    register_power8_book4_sprs(env);
> +    register_power9_book4_sprs(env);
>       register_power8_rpr_sprs(env);
>       register_power9_mmu_sprs(env);
>       register_power10_hash_sprs(env);


  reply	other threads:[~2023-06-30 19:37 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-25 12:03 [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Nicholas Piggin
2023-06-25 12:03 ` [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Nicholas Piggin
2023-06-30 19:36   ` Daniel Henrique Barboza [this message]
2023-06-25 12:03 ` [PATCH 2/2] target/ppc: Add TFMR SPR implementation with read and write helpers Nicholas Piggin
2023-06-30 19:36   ` Daniel Henrique Barboza
2023-06-29  4:58 ` [PATCH 0/2] target/ppc: Easy parts of the POWER chiptod series Cédric Le Goater
2023-06-30 19:38   ` Daniel Henrique Barboza
2023-07-01  8:38     ` Nicholas Piggin
2023-07-01  9:03       ` Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1d6fed0b-1338-d359-89af-9a4e30e97589@gmail.com \
    --to=danielhb413@gmail.com \
    --cc=clg@kaod.org \
    --cc=harshpb@linux.ibm.com \
    --cc=npiggin@gmail.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).