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[201.69.66.110]) by smtp.gmail.com with ESMTPSA id es20-20020a056808279400b003a054ec1d90sm6989966oib.6.2023.06.30.12.36.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Jun 2023 12:36:20 -0700 (PDT) Message-ID: <1d6fed0b-1338-d359-89af-9a4e30e97589@gmail.com> Date: Fri, 30 Jun 2023 16:36:17 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH 1/2] target/ppc: Tidy POWER book4 SPR registration Content-Language: en-US To: Nicholas Piggin , qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Harsh Prateek Bora References: <20230625120317.13877-1-npiggin@gmail.com> <20230625120317.13877-2-npiggin@gmail.com> From: Daniel Henrique Barboza In-Reply-To: <20230625120317.13877-2-npiggin@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.095, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/25/23 09:03, Nicholas Piggin wrote: > POWER book4 (implementation-specific) SPRs are sometimes in their own > functions, but in other cases are mixed with architected SPRs. Do some > spring cleaning on these. > > Reviewed-by: Cédric Le Goater > Signed-off-by: Nicholas Piggin > --- Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel > target/ppc/cpu_init.c | 82 +++++++++++++++++++++++++++++-------------- > 1 file changed, 55 insertions(+), 27 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index a97fb7fe10..21ff4861c3 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -5370,31 +5370,6 @@ static void register_book3s_ids_sprs(CPUPPCState *env) > &spr_read_generic, SPR_NOACCESS, > &spr_read_generic, NULL, > 0x00000000); > - spr_register_hv(env, SPR_HID0, "HID0", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > - 0x00000000); > - spr_register_hv(env, SPR_TSCR, "TSCR", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic32, > - 0x00000000); > - spr_register_hv(env, SPR_HMER, "HMER", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_hmer, > - 0x00000000); > - spr_register_hv(env, SPR_HMEER, "HMEER", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > - 0x00000000); > - spr_register_hv(env, SPR_TFMR, "TFMR", > - SPR_NOACCESS, SPR_NOACCESS, > - SPR_NOACCESS, SPR_NOACCESS, > - &spr_read_generic, &spr_write_generic, > - 0x00000000); > spr_register_hv(env, SPR_LPIDR, "LPIDR", > SPR_NOACCESS, SPR_NOACCESS, > SPR_NOACCESS, SPR_NOACCESS, > @@ -5656,14 +5631,60 @@ static void register_power8_ic_sprs(CPUPPCState *env) > #endif > } > > +/* SPRs specific to IBM POWER CPUs */ > +static void register_power_common_book4_sprs(CPUPPCState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + spr_register_hv(env, SPR_HID0, "HID0", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_TSCR, "TSCR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic32, > + 0x00000000); > + spr_register_hv(env, SPR_HMER, "HMER", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_hmer, > + 0x00000000); > + spr_register_hv(env, SPR_HMEER, "HMEER", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > + spr_register_hv(env, SPR_TFMR, "TFMR", > + SPR_NOACCESS, SPR_NOACCESS, > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + 0x00000000); > +#endif > +} > + > +static void register_power9_book4_sprs(CPUPPCState *env) > +{ > + /* Add a number of P9 book4 registers */ > + register_power_common_book4_sprs(env); > +#if !defined(CONFIG_USER_ONLY) > + spr_register_kvm(env, SPR_WORT, "WORT", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + KVM_REG_PPC_WORT, 0); > +#endif > +} > + > static void register_power8_book4_sprs(CPUPPCState *env) > { > /* Add a number of P8 book4 registers */ > + register_power_common_book4_sprs(env); > #if !defined(CONFIG_USER_ONLY) > spr_register_kvm(env, SPR_ACOP, "ACOP", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_ACOP, 0); > + /* PID is only in BookE in ISA v2.07 */ > spr_register_kvm(env, SPR_BOOKS_PID, "PID", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_pidr, > @@ -5679,10 +5700,12 @@ static void register_power7_book4_sprs(CPUPPCState *env) > { > /* Add a number of P7 book4 registers */ > #if !defined(CONFIG_USER_ONLY) > + register_power_common_book4_sprs(env); > spr_register_kvm(env, SPR_ACOP, "ACOP", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > KVM_REG_PPC_ACOP, 0); > + /* PID is only in BookE in ISA v2.06 */ > spr_register_kvm(env, SPR_BOOKS_PID, "PID", > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic32, > @@ -5716,6 +5739,11 @@ static void register_power9_mmu_sprs(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > 0x0000000000000000); > + /* PID is part of the BookS ISA from v3.0 */ > + spr_register_kvm(env, SPR_BOOKS_PID, "PID", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_pidr, > + KVM_REG_PPC_PID, 0); > #endif > } > > @@ -6269,7 +6297,7 @@ static void init_proc_POWER9(CPUPPCState *env) > register_power8_dpdes_sprs(env); > register_vtb_sprs(env); > register_power8_ic_sprs(env); > - register_power8_book4_sprs(env); > + register_power9_book4_sprs(env); > register_power8_rpr_sprs(env); > register_power9_mmu_sprs(env); > > @@ -6462,7 +6490,7 @@ static void init_proc_POWER10(CPUPPCState *env) > register_power8_dpdes_sprs(env); > register_vtb_sprs(env); > register_power8_ic_sprs(env); > - register_power8_book4_sprs(env); > + register_power9_book4_sprs(env); > register_power8_rpr_sprs(env); > register_power9_mmu_sprs(env); > register_power10_hash_sprs(env);