From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/4] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
Date: Mon, 20 May 2019 19:25:19 +0200 [thread overview]
Message-ID: <1d95fef3-b59d-69b2-5776-7494f74dbd0f@redhat.com> (raw)
In-Reply-To: <20190520162809.2677-4-peter.maydell@linaro.org>
On 5/20/19 6:28 PM, Peter Maydell wrote:
> In ich_vmcr_write() we enforce "writes of BPR fields to less than
> their minimum sets them to the minimum" by doing a "read vbpr and
> write it back" operation. A typo here meant that we weren't handling
> writes to these fields correctly, because we were reading from VBPR0
> but writing to VBPR1.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/intc/arm_gicv3_cpuif.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
> index cbad6037f19..000bdbd6247 100644
> --- a/hw/intc/arm_gicv3_cpuif.c
> +++ b/hw/intc/arm_gicv3_cpuif.c
> @@ -2366,7 +2366,7 @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> /* Enforce "writing BPRs to less than minimum sets them to the minimum"
> * by reading and writing back the fields.
> */
> - write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
> + write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
> write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
>
> gicv3_cpuif_virt_update(cs);
>
next prev parent reply other threads:[~2019-05-20 17:46 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-20 16:28 [Qemu-devel] [PATCH 0/4] hw/intc/arm_gicv3: Four simple bugfixes Peter Maydell
2019-05-20 16:28 ` [Qemu-devel] [PATCH 1/4] hw/intc/arm_gicv3: Fix decoding of ID register range Peter Maydell
2019-05-20 17:24 ` Philippe Mathieu-Daudé
2019-05-21 14:25 ` Peter Maydell
2019-05-20 16:28 ` [Qemu-devel] [PATCH 2/4] hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1 Peter Maydell
2019-05-20 16:28 ` [Qemu-devel] [PATCH 3/4] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} Peter Maydell
2019-05-20 17:25 ` Philippe Mathieu-Daudé [this message]
2019-05-20 16:28 ` [Qemu-devel] [PATCH 4/4] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3 Peter Maydell
2019-05-20 17:20 ` Philippe Mathieu-Daudé
2019-05-23 14:27 ` [Qemu-devel] [PATCH 0/4] hw/intc/arm_gicv3: Four simple bugfixes Peter Maydell
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