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[88.21.202.183]) by smtp.gmail.com with ESMTPSA id o13sm2884994wra.92.2019.06.21.07.09.32 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Fri, 21 Jun 2019 07:09:33 -0700 (PDT) To: Laurent Vivier , qemu-devel@nongnu.org References: <20190619221933.1981-1-laurent@vivier.eu> <20190619221933.1981-2-laurent@vivier.eu> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: <1de4d92a-4176-6584-0363-6f624ecb5af3@redhat.com> Date: Fri, 21 Jun 2019 16:09:32 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190619221933.1981-2-laurent@vivier.eu> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.221.67 Subject: Re: [Qemu-devel] [PATCH v8 01/10] escc: introduce a selector for the register bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Fam Zheng , qemu-block@nongnu.org, Thomas Huth , Jason Wang , Mark Cave-Ayland , "Dr . David Alan Gilbert" , Max Reitz , =?UTF-8?Q?Herv=c3=a9_Poussineau?= , Gerd Hoffmann , =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/20/19 12:19 AM, Laurent Vivier wrote: > On Sparc and PowerMac, the bit 0 of the address > selects the register type (control or data) and > bit 1 selects the channel (B or A). > > On m68k Macintosh, the bit 0 selects the channel and > bit 1 the register type. > > This patch introduces a new parameter (bit_swap) to > the device interface to indicate bits usage must > be swapped between registers and channels. > > For the moment all the machines use the bit 0, > but this change will be needed to emulate Quadra 800. I feel we are missing something and this model slowly becomes another Frankenstein. The SCC core is a monster anyway. I'm glad you could resolve your issue with this easy fix. > Signed-off-by: Laurent Vivier > Reviewed-by: Hervé Poussineau > Reviewed-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daudé > --- > hw/char/escc.c | 30 ++++++++++++++++++++++++------ > include/hw/char/escc.h | 1 + > 2 files changed, 25 insertions(+), 6 deletions(-) > > diff --git a/hw/char/escc.c b/hw/char/escc.c > index 8ddbb4be4f..2748bd62c3 100644 > --- a/hw/char/escc.c > +++ b/hw/char/escc.c > @@ -43,14 +43,21 @@ > * mouse and keyboard ports don't implement all functions and they are > * only asynchronous. There is no DMA. > * > - * Z85C30 is also used on PowerMacs. There are some small differences > - * between Sparc version (sunzilog) and PowerMac (pmac): > + * Z85C30 is also used on PowerMacs and m68k Macs. > + * > + * There are some small differences between Sparc version (sunzilog) > + * and PowerMac (pmac): > * Offset between control and data registers > * There is some kind of lockup bug, but we can ignore it > * CTS is inverted > * DMA on pmac using DBDMA chip > * pmac can do IRDA and faster rates, sunzilog can only do 38400 > * pmac baud rate generator clock is 3.6864 MHz, sunzilog 4.9152 MHz > + * > + * Linux driver for m68k Macs is the same as for PowerMac (pmac_zilog), > + * but registers are grouped by type and not by channel: > + * channel is selected by bit 0 of the address (instead of bit 1) > + * and register is selected by bit 1 of the address (instead of bit 0). > */ > > /* > @@ -170,6 +177,16 @@ static void handle_kbd_command(ESCCChannelState *s, int val); > static int serial_can_receive(void *opaque); > static void serial_receive_byte(ESCCChannelState *s, int ch); > > +static int reg_shift(ESCCState *s) > +{ > + return s->bit_swap ? s->it_shift + 1 : s->it_shift; > +} > + > +static int chn_shift(ESCCState *s) > +{ > + return s->bit_swap ? s->it_shift : s->it_shift + 1; > +} > + > static void clear_queue(void *opaque) > { > ESCCChannelState *s = opaque; > @@ -434,8 +451,8 @@ static void escc_mem_write(void *opaque, hwaddr addr, > int newreg, channel; > > val &= 0xff; > - saddr = (addr >> serial->it_shift) & 1; > - channel = (addr >> (serial->it_shift + 1)) & 1; > + saddr = (addr >> reg_shift(serial)) & 1; > + channel = (addr >> chn_shift(serial)) & 1; > s = &serial->chn[channel]; > switch (saddr) { > case SERIAL_CTRL: > @@ -545,8 +562,8 @@ static uint64_t escc_mem_read(void *opaque, hwaddr addr, > uint32_t ret; > int channel; > > - saddr = (addr >> serial->it_shift) & 1; > - channel = (addr >> (serial->it_shift + 1)) & 1; > + saddr = (addr >> reg_shift(serial)) & 1; > + channel = (addr >> chn_shift(serial)) & 1; > s = &serial->chn[channel]; > switch (saddr) { > case SERIAL_CTRL: > @@ -830,6 +847,7 @@ static void escc_realize(DeviceState *dev, Error **errp) > static Property escc_properties[] = { > DEFINE_PROP_UINT32("frequency", ESCCState, frequency, 0), > DEFINE_PROP_UINT32("it_shift", ESCCState, it_shift, 0), > + DEFINE_PROP_BOOL("bit_swap", ESCCState, bit_swap, false), > DEFINE_PROP_UINT32("disabled", ESCCState, disabled, 0), > DEFINE_PROP_UINT32("chnBtype", ESCCState, chn[0].type, 0), > DEFINE_PROP_UINT32("chnAtype", ESCCState, chn[1].type, 0), > diff --git a/include/hw/char/escc.h b/include/hw/char/escc.h > index 42aca83611..8762f61c14 100644 > --- a/include/hw/char/escc.h > +++ b/include/hw/char/escc.h > @@ -50,6 +50,7 @@ typedef struct ESCCState { > > struct ESCCChannelState chn[2]; > uint32_t it_shift; > + bool bit_swap; > MemoryRegion mmio; > uint32_t disabled; > uint32_t frequency; >