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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e56f658ffsm5662925e9.14.2025.09.29.02.46.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Sep 2025 02:46:42 -0700 (PDT) Message-ID: <1e08caeb-1cf9-4864-a3d0-6d9b3857f2a3@linaro.org> Date: Mon, 29 Sep 2025 11:46:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 3/5] hw/arm/npcm8xx.c: Add all IRQ ENUMs Content-Language: en-US To: Coco Li Cc: peter.maydell@linaro.org, clg@kaod.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org, flwu@google.com, andrew@codeconstruct.com.au, Hao Wu References: <20250925005832.3708492-1-lixiaoyan@google.com> <20250925005832.3708492-4-lixiaoyan@google.com> <1a755fbf-e6d6-4f80-b35d-29fcb3f587d3@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 26/9/25 23:48, Coco Li wrote: > Hi Phil, > > Thanks for the review! > It looks like IRQ mapping enums on other boards also generally do not > have line breaks, is it ok if I keep it like this for consistency sake? This is just a suggestion, since you are modifying these lines. I won't object if you keep the old style, and I don't mind if the other boards as not changed (also, can be done as future cleanup). (please avoid top-posting on technical mailing lists). > > Best, > Coco > > On Wed, Sep 24, 2025 at 6:08 PM Philippe Mathieu-Daudé > > wrote: > > Hi, > > On 25/9/25 02:58, Coco Li wrote: > > In the process of implementing serial gpio and adding the > corresponding > > ENUMs, also complete the list for npcm8xx. > > > > Signed-off-by: Coco Li > > > Reviewed-by: Hao Wu > > > --- > >   hw/arm/npcm8xx.c | 43 ++++++++++++++++++++++++++++++++++++++++++- > >   1 file changed, 42 insertions(+), 1 deletion(-) > > > > diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c > > index a276fea698..10887d07fa 100644 > > --- a/hw/arm/npcm8xx.c > > +++ b/hw/arm/npcm8xx.c > > @@ -92,8 +92,14 @@ enum NPCM8xxInterrupt { > >       NPCM8XX_GMAC2_IRQ, > >       NPCM8XX_GMAC3_IRQ, > >       NPCM8XX_GMAC4_IRQ, > > -    NPCM8XX_MMC_IRQ             = 26, > > +    NPCM8XX_ESPI_IRQ, > > +    NPCM8XX_SIOX0_IRQ, > > +    NPCM8XX_SIOX1_IRQ, > > +    NPCM8XX_MC_IRQ              = 25, > > +    NPCM8XX_MMC_IRQ, > >       NPCM8XX_PSPI_IRQ            = 28, > > +    NPCM8XX_VDMA_IRQ, > > +    NPCM8XX_MCTP_IRQ, > >       NPCM8XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */ > >       NPCM8XX_TIMER1_IRQ, > >       NPCM8XX_TIMER2_IRQ, > > @@ -116,6 +122,14 @@ enum NPCM8xxInterrupt { > >       NPCM8XX_OHCI1_IRQ, > >       NPCM8XX_EHCI2_IRQ, > >       NPCM8XX_OHCI2_IRQ, > > +    NPCM8XX_SPI1_IRQ            = 82, > > +    NPCM8XX_RNG_IRQ             = 84, > > +    NPCM8XX_SPI0_IRQ            = 85, > > +    NPCM8XX_SPI3_IRQ            = 87, > > +    NPCM8XX_GDMA0_IRQ           = 88, > > +    NPCM8XX_GDMA1_IRQ, > > +    NPCM8XX_GDMA2_IRQ, > > +    NPCM8XX_OTP_IRQ             = 92, > >       NPCM8XX_PWM0_IRQ            = 93,   /* PWM module 0 */ > >       NPCM8XX_PWM1_IRQ,                   /* PWM module 1 */ > >       NPCM8XX_MFT0_IRQ            = 96,   /* MFT module 0 */ > > @@ -128,6 +142,11 @@ enum NPCM8xxInterrupt { > >       NPCM8XX_MFT7_IRQ,                   /* MFT module 7 */ > >       NPCM8XX_PCI_MBOX1_IRQ       = 105, > >       NPCM8XX_PCI_MBOX2_IRQ, > > +    NPCM8XX_GPIO231_IRQ         = 108, > > +    NPCM8XX_GPIO233_IRQ, > > +    NPCM8XX_GPIO234_IRQ, > > +    NPCM8XX_GPIO93_IRQ, > > +    NPCM8XX_GPIO94_IRQ, > >       NPCM8XX_GPIO0_IRQ           = 116, > >       NPCM8XX_GPIO1_IRQ, > >       NPCM8XX_GPIO2_IRQ, > > @@ -163,6 +182,12 @@ enum NPCM8xxInterrupt { > >       NPCM8XX_SMBUS24_IRQ, > >       NPCM8XX_SMBUS25_IRQ, > >       NPCM8XX_SMBUS26_IRQ, > > +    NPCM8XX_FLM0_IRQ            = 160, > > +    NPCM8XX_FLM1_IRQ, > > +    NPCM8XX_FLM2_IRQ, > > +    NPCM8XX_FLM3_IRQ, > > Minor style comment, maybe worth adding a new line when the > following enum is not contiguous. > > Regards, > > Phil.