qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Richard Henderson <richard.henderson@linaro.org>
To: Andrew Jones <drjones@redhat.com>,
	qemu-devel@nongnu.org, qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, armbru@redhat.com,
	eric.auger@redhat.com, imammedo@redhat.com,
	alex.bennee@linaro.org, Dave.Martin@arm.com
Subject: Re: [Qemu-devel] [PATCH v2 10/14] target/arm/kvm64: Add kvm_arch_get/put_sve
Date: Wed, 26 Jun 2019 17:22:34 +0200	[thread overview]
Message-ID: <1e0bc93f-42e3-087f-a4b5-d356879cb806@linaro.org> (raw)
In-Reply-To: <20190621163422.6127-11-drjones@redhat.com>

On 6/21/19 6:34 PM, Andrew Jones wrote:
> +/*
> + * If ARM_MAX_VQ is increased to be greater than 16, then we can no
> + * longer hard code slices to 1 in kvm_arch_put/get_sve().
> + */
> +QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);

This seems easy to fix, or simply drop the slices entirely for now, as
otherwise they are a teeny bit confusing.

It's a shame that these slices exist at all.  It seems like the kernel could
use the negotiated max sve size to grab the data all at once.

> +        for (n = 0; n < KVM_ARM64_SVE_NUM_ZREGS; n++) {
> +            uint64_t *q = aa64_vfp_qreg(env, n);
> +#ifdef HOST_WORDS_BIGENDIAN
> +            uint64_t d[ARM_MAX_VQ * 2];
> +            int j;
> +            for (j = 0; j < cpu->sve_max_vq * 2; j++) {
> +                d[j] = bswap64(q[j]);
> +            }
> +            reg.addr = (uintptr_t)d;
> +#else
> +            reg.addr = (uintptr_t)q;
> +#endif
> +            reg.id = KVM_REG_ARM64_SVE_ZREG(n, i);
> +            ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

It might be worth splitting this...

> +        for (n = 0; n < KVM_ARM64_SVE_NUM_PREGS; n++) {
> +            uint64_t *q = &env->vfp.pregs[n].p[0];
> +#ifdef HOST_WORDS_BIGENDIAN
> +            uint64_t d[ARM_MAX_VQ * 2 / 8];
> +            int j;
> +            for (j = 0; j < cpu->sve_max_vq * 2 / 8; j++) {
> +                d[j] = bswap64(q[j]);
> +            }
> +            reg.addr = (uintptr_t)d;
> +#else
> +            reg.addr = (uintptr_t)q;
> +#endif
> +            reg.id = KVM_REG_ARM64_SVE_PREG(n, i);
> +            ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

... and this (unified w/ reg + size parameters?) to a function because ...

> +        reg.addr = (uintptr_t)&env->vfp.pregs[FFR_PRED_NUM].p[0];
> +        reg.id = KVM_REG_ARM64_SVE_FFR(i);
> +        ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);

... you forgot to apply the bswap here.

Likewise for the other direction.


r~


PS: It's also tempting to drop the ifdefs and, since we know the host supports
sve instructions, and that the host supports sve_max_vq, do the reformatting as

    uint64_t scratch[ARM_MAX_VQ * 2];
    asm("whilelo  p0.d, xzr, %2\n\t"
        "ld1d     z0.d, p0/z [%1]\n\t"
        "str      z0, [%0]"
        : "=Q"(scratch)
        : "Q"(*aa64_vfp_qreg(env, n)),
          "r"(cpu->sve_max_vq)
        : "p0", "v0");

PPS: Ideally, this would be further cleaned up with acle builtins, but those
are still under development for GCC.


  parent reply	other threads:[~2019-06-26 18:39 UTC|newest]

Thread overview: 95+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-21 16:34 [Qemu-devel] [PATCH v2 00/14] target/arm/kvm: enable SVE in guests Andrew Jones
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 01/14] target/arm/cpu64: Ensure kvm really supports aarch64=off Andrew Jones
2019-06-25  9:35   ` Auger Eric
2019-06-25 13:34     ` Andrew Jones
2019-07-24 12:51       ` Auger Eric
2019-07-24 13:52         ` Andrew Jones
2019-07-24 14:19           ` Auger Eric
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 02/14] target/arm/cpu: Ensure we can use the pmu with kvm Andrew Jones
2019-06-25  9:35   ` Auger Eric
2019-06-26  9:49   ` Richard Henderson
2019-06-26 13:11     ` Andrew Jones
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 03/14] target/arm/monitor: Introduce qmp_query_cpu_model_expansion Andrew Jones
2019-06-26  7:43   ` Auger Eric
2019-06-26 13:26     ` Andrew Jones
2019-07-24 12:51       ` Auger Eric
2019-07-24 14:05         ` Andrew Jones
2019-07-24 14:25           ` Auger Eric
2019-07-24 14:44             ` Andrew Jones
2019-07-24 12:55       ` Auger Eric
2019-07-24 14:13         ` Andrew Jones
2019-07-25  8:04   ` Auger Eric
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 04/14] tests: arm: Introduce cpu feature tests Andrew Jones
2019-07-25  7:54   ` Auger Eric
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 05/14] target/arm/helper: zcr: Add build bug next to value range assumption Andrew Jones
2019-06-24 11:05   ` Dave Martin
2019-06-24 11:30     ` Andrew Jones
2019-06-24 16:03       ` Dave Martin
2019-06-25  6:11         ` Andrew Jones
2019-06-25  6:14           ` Andrew Jones
2019-06-26 10:01   ` Auger Eric
2019-06-26 13:28     ` Andrew Jones
2019-06-26 13:40       ` Auger Eric
2019-06-26 13:58         ` Andrew Jones
2019-06-26 14:06           ` Auger Eric
2019-06-26 10:07   ` Richard Henderson
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 06/14] target/arm: Allow SVE to be disabled via a CPU property Andrew Jones
2019-06-21 16:55   ` Philippe Mathieu-Daudé
2019-06-21 17:11     ` Andrew Jones
2019-06-26 10:00   ` Auger Eric
2019-06-26 13:38     ` Andrew Jones
2019-06-26 10:20   ` Richard Henderson
2019-06-26 13:52     ` Andrew Jones
2019-07-17 15:43       ` Andrew Jones
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 07/14] target/arm/cpu64: max cpu: Introduce sve<vl-bits> properties Andrew Jones
2019-06-24 11:05   ` Dave Martin
2019-06-24 11:49     ` Andrew Jones
2019-06-24 12:10       ` Andrew Jones
2019-06-24 16:06         ` Dave Martin
2019-06-26 14:58   ` Auger Eric
2019-06-27  9:40     ` Andrew Jones
2019-06-27 10:51       ` Auger Eric
2019-06-27 11:43         ` Andrew Jones
2019-06-26 16:56   ` Auger Eric
2019-06-27 10:46     ` Andrew Jones
2019-06-27 11:00       ` Auger Eric
2019-06-27 11:47         ` Andrew Jones
2019-06-27 15:16           ` Dave Martin
2019-06-27 16:19             ` Richard Henderson
2019-06-27 16:49   ` Richard Henderson
2019-06-28  7:27     ` Andrew Jones
2019-06-28  8:31       ` Andrew Jones
2019-06-29  0:10       ` Richard Henderson
2019-07-17  8:13         ` Andrew Jones
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 08/14] target/arm/kvm64: Fix error returns Andrew Jones
2019-06-26 10:53   ` Richard Henderson
2019-06-26 11:50   ` Richard Henderson
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 09/14] target/arm/kvm64: Move the get/put of fpsimd registers out Andrew Jones
2019-06-26 10:35   ` Richard Henderson
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 10/14] target/arm/kvm64: Add kvm_arch_get/put_sve Andrew Jones
2019-06-24 11:05   ` Dave Martin
2019-06-24 11:55     ` Andrew Jones
2019-06-24 16:09       ` Dave Martin
2019-06-26 15:22   ` Richard Henderson [this message]
2019-06-27 10:59     ` Dave Martin
2019-06-27 11:26       ` Richard Henderson
2019-06-27 15:02         ` Dave Martin
2019-07-17  9:25           ` Andrew Jones
2019-07-17  9:35     ` Andrew Jones
2019-06-27  6:56   ` Auger Eric
2019-06-27 10:59     ` Andrew Jones
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 11/14] target/arm/kvm64: max cpu: Enable SVE when available Andrew Jones
2019-06-26 11:09   ` Richard Henderson
2019-06-27 11:56     ` Andrew Jones
2019-06-28 16:14   ` Auger Eric
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 12/14] target/arm/kvm: scratch vcpu: Preserve input kvm_vcpu_init features Andrew Jones
2019-06-26 11:11   ` Richard Henderson
2019-06-27  7:30   ` Auger Eric
2019-06-27 10:53     ` Andrew Jones
2019-06-27 11:01     ` Dave Martin
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 13/14] target/arm/cpu64: max cpu: Support sve properties with KVM Andrew Jones
2019-06-28 15:55   ` Auger Eric
2019-07-17  8:41     ` Andrew Jones
2019-06-21 16:34 ` [Qemu-devel] [PATCH v2 14/14] target/arm/kvm: host cpu: Add support for sve<vl-bits> properties Andrew Jones
2019-06-27 17:15   ` Auger Eric
2019-06-28  7:05     ` Andrew Jones

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1e0bc93f-42e3-087f-a4b5-d356879cb806@linaro.org \
    --to=richard.henderson@linaro.org \
    --cc=Dave.Martin@arm.com \
    --cc=alex.bennee@linaro.org \
    --cc=armbru@redhat.com \
    --cc=drjones@redhat.com \
    --cc=eric.auger@redhat.com \
    --cc=imammedo@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).