From: Richard Henderson <richard.henderson@linaro.org>
To: "Clément Chigot" <chigot@adacore.com>
Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Idan Horowitz" <idan.horowitz@gmail.com>,
"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>,
ardb@kernel.org
Subject: Re: [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled
Date: Mon, 22 Apr 2024 08:47:44 -0700 [thread overview]
Message-ID: <1e4cd671-45fe-4a97-8f76-5bbb07a84c15@linaro.org> (raw)
In-Reply-To: <CAJ307Egu6951WwbdoTERUVff9cr=2qBK70FWgk3Ck-1DCpDtHA@mail.gmail.com>
On 4/22/24 08:26, Clément Chigot wrote:
> Hi Richard,
>
> While testing the future V9, I've some regressions on a custom board
> using cortex-R5 CPUs.
> Unaligned data accesses are no longer allowed because of that patch.
>
> I've dug into the various documentation and it seems that R-profile
> CPUs don't have the same default memory type as A-profile. It depends
> on a default memory map provided in the R-Profile RM in C1.3 [1], even
> when PMU is disabled.
>
>> Each PMSAv8-32 MPU has an associated default memory map which is used when the MPU is not enabled.
>> ...
>> Table C1-4 and Table C1-5 describe the default memory map defined for the EL1 MPU.
>
> For our case, Table C1-5 can be simplified as:
> | 0x00000000 – 0x7FFFFFFF Normal
> | 0x80000000 – 0xBFFFFFFF Device-nGnRE
> | 0xC0000000 – 0xFFFFFFFF Device-nGnRnE
>
> Therefore, we can't blindly enable strict alignment checking solely on
> SCTLR bits. We should make it depend on the address targeted. But is
> it possible to know that address in `aprofile_require_alignment` ?
> with `mmu_idx` ?
No, this would need to be handled in get_phys_addr_disabled.
> By the way, are R-Profile CPUs the same as those having the `PMSA`
> feature ? That could mean we can use the `ARM_FEATURE_PMSA` to deal
> with that, instead of create a new `ARM_FEATURE_R`
No, some armv5 have PMSA.
>
> Note that the RM I've linked is for ARMv8. But this other link [2]
> seems to show a similar behavior for arm-v7.
>
> cc Jonathan and Ard, though not sure this is the same bug you've
> reported earlier.
>
> Thanks,
> Clément
> [1] https://developer.arm.com/documentation/ddi0568/a-c/?lang=en
> [2] https://developer.arm.com/documentation/ddi0406/cb/System-Level-Architecture/Protected-Memory-System-Architecture--PMSA-/About-the-PMSA/Enabling-and-disabling-the-MPU?lang=en#BEIJEFCJ
Ouch, thanks for the armv7 link. At the moment it looks like my blanket mmu-disabled
change should be restricted to armv8.
r~
next prev parent reply other threads:[~2024-04-22 15:48 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-01 20:41 [PATCH v3 0/6] target/arm: Do memory alignment check for device memory Richard Henderson
2024-03-01 20:41 ` [PATCH v3 1/6] target/arm: Support 32-byte alignment in pow2_align Richard Henderson
2024-03-01 20:41 ` [PATCH v3 2/6] exec/memattrs: Remove target_tlb_bit* Richard Henderson
2024-03-01 20:41 ` [PATCH v3 3/6] accel/tcg: Add tlb_fill_flags to CPUTLBEntryFull Richard Henderson
2024-03-01 20:41 ` [PATCH v3 4/6] accel/tcg: Add TLB_CHECK_ALIGNED Richard Henderson
2024-03-01 20:41 ` [PATCH v3 5/6] target/arm: Do memory type alignment check when translation disabled Richard Henderson
2024-04-16 15:11 ` Jonathan Cameron via
2024-04-17 20:07 ` Richard Henderson
2024-04-18 8:15 ` Jonathan Cameron via
2024-04-18 17:40 ` Jonathan Cameron via
2024-04-19 11:52 ` [edk2-devel] " Gerd Hoffmann
2024-04-19 16:09 ` Jonathan Cameron via
2024-04-19 16:36 ` Ard Biesheuvel
2024-04-19 17:38 ` Ard Biesheuvel
2024-04-22 15:26 ` Clément Chigot
2024-04-22 15:47 ` Richard Henderson [this message]
2024-04-22 15:59 ` Peter Maydell
2024-03-01 20:41 ` [PATCH v3 6/6] target/arm: Do memory type alignment check when translation enabled Richard Henderson
2024-03-04 17:10 ` Peter Maydell
2024-03-04 17:27 ` Richard Henderson
2024-03-04 17:12 ` [PATCH v3 0/6] target/arm: Do memory alignment check for device memory Peter Maydell
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