From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 3/5] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
Date: Fri, 11 Sep 2020 12:30:20 -0700 [thread overview]
Message-ID: <1e58a799-6380-ee78-9a4b-291f3e100596@linaro.org> (raw)
In-Reply-To: <20200910173855.4068-4-peter.maydell@linaro.org>
On 9/10/20 10:38 AM, Peter Maydell wrote:
> M-profile CPUs only implement the ID registers as guest-visible if
> the CPU implements the Main Extension (all our current CPUs except
> the Cortex-M0 do).
>
> Currently we handle this by having the Cortex-M0 leave the ID
> register values in the ARMCPU struct as zero, but this conflicts with
> our design decision to make QEMU behaviour be keyed off ID register
> fields wherever possible.
>
> Explicitly code the ID registers in the NVIC to return 0 if the Main
> Extension is not implemented, so we can make the M0 model set the
> ARMCPU struct fields to obtain the correct behaviour without those
> values becoming guest-visible.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2020-09-11 19:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-10 17:38 [PATCH 0/5] handle M-profile in fp16_arith isar_feature test Peter Maydell
2020-09-10 17:38 ` [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check Peter Maydell
2020-09-11 19:27 ` Richard Henderson
2020-09-10 17:38 ` [PATCH 2/5] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters Peter Maydell
2020-09-11 19:28 ` Richard Henderson
2020-09-10 17:38 ` [PATCH 3/5] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs Peter Maydell
2020-09-11 19:30 ` Richard Henderson [this message]
2020-09-10 17:38 ` [PATCH 4/5] target/arm: Add ID register values for Cortex-M0 Peter Maydell
2020-09-11 19:31 ` Richard Henderson
2020-09-10 17:38 ` [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile Peter Maydell
2020-09-11 19:32 ` Richard Henderson
2020-09-11 19:40 ` [PATCH 0/5] handle M-profile in fp16_arith isar_feature test Richard Henderson
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