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From: Peng Liang <liangpeng10@huawei.com>
To: Andrew Jones <drjones@redhat.com>
Cc: peter.maydell@linaro.org,
	Zhanghailiang <zhang.zhanghailiang@huawei.com>,
	mst@redhat.com, cohuck@redhat.com, qemu-devel@nongnu.org,
	xiexiangyou 00584000 <xiexiangyou@huawei.com>,
	qemu-arm@nongnu.org, pbonzini@redhat.com,
	zhukeqian 00502301 <zhukeqian1@huawei.com>
Subject: Re: [RFC 5/9] target/arm: introduce CPU feature dependency mechanism
Date: Sat, 15 Aug 2020 10:19:27 +0800	[thread overview]
Message-ID: <1e7160d1-96e7-7581-cdc9-cb4ad44aca72@huawei.com> (raw)
In-Reply-To: <20200813124821.psavdkhddg4duar6@kamzik.brq.redhat.com>

On 8/13/2020 8:48 PM, Andrew Jones wrote:
> On Thu, Aug 13, 2020 at 06:26:53PM +0800, Peng Liang wrote:
>> Some CPU features are dependent on other CPU features.  For example,
>> ID_AA64PFR0_EL1.FP field and ID_AA64PFR0_EL1.AdvSIMD must have the same
>> value, which means FP and ADVSIMD are dependent on each other, FPHP and
>> ADVSIMDHP are dependent on each other.
>>
>> This commit introduces a mechanism for CPU feature dependency in
>> AArch64.  We build a directed graph from the CPU feature dependency
>> relationship, each edge from->to means the `to` CPU feature is dependent
>> on the `from` CPU feature.  And we will automatically enable/disable CPU
>> feature according to the directed graph.
>>
>> For example, a, b, and c CPU features are in relationship a->b->c, which
>> means c is dependent on b and b is dependent on a.  If c is enabled by
>> user, then a and b is enabled automatically.  And if a is disabled by
>> user, then b and c is disabled automatically.
> 
> And what if a is mutually exclusive with b? I.e. a and b can both be
> disabled, but only a or b may be enabled.
> 
> Thanks,
> drew
> 
> .
> 

Currently, a and b will be both enabled or disabled.  For example, a and b are
in relationship a->b, which means b is dependent on a.  If -cpu host,a=off,b=on,
then both a and b are enabled.  If -cpu host,b=on,a=off, then both a and b are
disabled.  Maybe we should report an error to user in this scenario?

Thanks,
Peng


  reply	other threads:[~2020-08-15 18:12 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-13 10:26 [RFC 0/9] Support disable/enable CPU features for AArch64 Peng Liang
2020-08-13 10:26 ` [RFC 1/9] target/arm: convert isar regs to array Peng Liang
2020-08-13 10:42   ` Philippe Mathieu-Daudé
2020-08-13 16:11     ` Richard Henderson
2020-08-13 10:26 ` [RFC 2/9] target/arm: parse cpu feature related options Peng Liang
2020-08-13 12:21   ` Andrew Jones
2020-08-15  2:19     ` Peng Liang
2020-08-15  6:51       ` Andrew Jones
2020-08-13 10:26 ` [RFC 3/9] target/arm: register CPU features for property Peng Liang
2020-08-13 12:34   ` Andrew Jones
2020-08-13 10:26 ` [RFC 4/9] target/arm: Allow ID registers to synchronize to KVM Peng Liang
2020-08-13 10:26 ` [RFC 5/9] target/arm: introduce CPU feature dependency mechanism Peng Liang
2020-08-13 12:48   ` Andrew Jones
2020-08-15  2:19     ` Peng Liang [this message]
2020-08-15  6:59       ` Andrew Jones
2020-08-13 10:26 ` [RFC 6/9] target/arm: introduce KVM_CAP_ARM_CPU_FEATURE Peng Liang
2020-08-13 11:00   ` Cornelia Huck
2020-08-15  2:19     ` Peng Liang
2020-08-13 10:26 ` [RFC 7/9] target/arm: Add CPU features to query-cpu-model-expansion Peng Liang
2020-08-13 12:56   ` Andrew Jones
2020-08-15  2:19     ` Peng Liang
2020-08-15  7:02       ` Andrew Jones
2020-08-13 10:26 ` [RFC 8/9] target/arm: Update ID fields Peng Liang
2020-08-13 10:26 ` [RFC 9/9] target/arm: Add more CPU features Peng Liang
2020-08-13 14:10 ` [RFC 0/9] Support disable/enable CPU features for AArch64 Andrew Jones
2020-08-13 16:30 ` no-reply
2020-08-13 16:34 ` no-reply
2020-08-13 16:38 ` no-reply

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