* [PATCH] target/mips: Align vector registers to 16 bytes
@ 2021-12-17 23:34 Philippe Mathieu-Daudé
2021-12-18 2:09 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-12-17 23:34 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno,
Philippe Mathieu-Daudé
Align fpr_t to 16 bytes to be able to use the TCG "Generic"
vector operation expansion API from "tcg/tcg-op-gvec.h",
otherwise we trigger assertions in check_size_align().
See commits ec8e23e37f8 (s390x) and 11e2bfef799 (i386)
for similar justifications.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 56b1cbd091d..15b983f7104 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -30,7 +30,7 @@ union fpr_t {
uint32_t w[2]; /* binary single fixed-point */
/* FPU/MSA register mapping is not tested on big-endian hosts. */
wr_t wr; /* vector data */
-};
+} QEMU_ALIGNED(16);
/*
*define FP_ENDIAN_IDX to access the same location
* in the fpr_t union regardless of the host endianness
--
2.33.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/mips: Align vector registers to 16 bytes
2021-12-17 23:34 [PATCH] target/mips: Align vector registers to 16 bytes Philippe Mathieu-Daudé
@ 2021-12-18 2:09 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2021-12-18 2:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 12/17/21 3:34 PM, Philippe Mathieu-Daudé wrote:
> Align fpr_t to 16 bytes to be able to use the TCG "Generic"
> vector operation expansion API from "tcg/tcg-op-gvec.h",
> otherwise we trigger assertions in check_size_align().
>
> See commits ec8e23e37f8 (s390x) and 11e2bfef799 (i386)
> for similar justifications.
>
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-12-18 2:10 UTC | newest]
Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-12-17 23:34 [PATCH] target/mips: Align vector registers to 16 bytes Philippe Mathieu-Daudé
2021-12-18 2:09 ` Richard Henderson
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).