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Wed, 20 Oct 2021 10:47:39 -0700 (PDT) Subject: Re: [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions To: =?UTF-8?B?RnLDqWTDqXJpYyBQw6l0cm90?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20211019094812.614056-1-frederic.petrot@univ-grenoble-alpes.fr> <20211019094812.614056-12-frederic.petrot@univ-grenoble-alpes.fr> From: Richard Henderson Message-ID: <1eb7ef2b-b636-3c93-a2d3-4d498da9865d@gmail.com> Date: Wed, 20 Oct 2021 10:47:36 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <20211019094812.614056-12-frederic.petrot@univ-grenoble-alpes.fr> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=rth7680@gmail.com; helo=mail-pf1-x429.google.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, NICE_REPLY_A=-2.267, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: philmd@redhat.com, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com, fabien.portas@grenoble-inp.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 10/19/21 2:48 AM, Frédéric Pétrot wrote: > The 128-bit bitwise instructions do not need any function prototype change > as the functions can be applied independently on the lower and upper part of > the registers. > > Signed-off-by: Frédéric Pétrot > Co-authored-by: Fabien Portas > --- > target/riscv/translate.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index e8f08f921e..71982f6284 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -429,6 +429,17 @@ static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, > > gen_set_gpr(ctx, a->rd, dest); > > + if (get_xl_max(ctx) == MXL_RV128) { > + if (get_ol(ctx) == MXL_RV128) { > + uint64_t immh = -(a->imm < 0); > + src1 = get_gprh(ctx, a->rs1); > + dest = dest_gprh(ctx, a->rd); > + > + func(dest, src1, immh); > + } > + gen_set_gprh(ctx, a->rd, dest); > + } If ol < RV128, you're storing the low dest into the gprh, which is wrong. It should be the sign-extension of the low part. But that should happen for all writes. Earlier, I suggested gen_set_gpr128 instead of gen_set_gprh. I think this should be written if (get_xl(ctx) == MXL_RV128) { TCGv src1h = get_gprh(ctx, a->rs1); TCGv desth = dest_gprh(ctx, a->rd); func(dest, src1h, -(a->imm < 0)); gen_set_gpr128(ctx, a->rd, dest, desth); } else { gen_set_gpr(ctx, a->rd, dest); } Where gen_set_gpr will handle the sign-extension to 128-bits. > @@ -443,6 +454,17 @@ static bool gen_logic(DisasContext *ctx, arg_r *a, DisasExtend ext, > > gen_set_gpr(ctx, a->rd, dest); > > + if (get_xl_max(ctx) == MXL_RV128) { > + if (get_ol(ctx) == MXL_RV128) { > + dest = dest_gprh(ctx, a->rd); > + src1 = get_gprh(ctx, a->rs1); > + src2 = get_gprh(ctx, a->rs2); > + > + func(dest, src1, src2); > + } > + gen_set_gprh(ctx, a->rd, dest); > + } Similarly. r~