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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id p6-20020a17090ac00600b002366c766ef4sm165474pjt.33.2023.02.23.14.01.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 23 Feb 2023 14:01:12 -0800 (PST) Message-ID: <1ecf3d94-8e0e-94fd-51a0-7772ea8cb786@linaro.org> Date: Thu, 23 Feb 2023 12:01:08 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH qemu 1/1] target/i386: Fix gen_shift_rm_T1, wrong eflags calculation Content-Language: en-US To: ~vilenka , qemu-devel@nongnu.org Cc: philmd@linaro.org, pbonzini@redhat.com References: <167718710208.23058.11278141733696221981-1@git.sr.ht> From: Richard Henderson In-Reply-To: <167718710208.23058.11278141733696221981-1@git.sr.ht> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/23/23 11:13, ~vilenka wrote: > From: Vilen Kamalov > > gen_shift_rm_T1 in the uses wrong tmp0 register, eflags calculation uses tmp4 at target/i386/tcg/translate.c, line 5488 > `tcg_gen_mov_tl(cpu_cc_src, s->tmp4);` The line you quote only applies to the bit instructions, bt/bts/btr/btc, so your explanation is clearly incorrect. > push rcx > mov dword ptr [rsp], 010000000h > mov rcx, 01eh > sar dword ptr [rsp], cl > jnc pass1 > int 3 > pass1: > mov dword ptr [rsp], 0ffffffffh > mov rcx, 01eh > sar dword ptr [rsp], cl > jc pass2 > int 3 > pass2: > pop rcx Thanks for the test case. > diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c > index 9d9392b009..9048e22868 100644 > --- a/target/i386/tcg/translate.c > +++ b/target/i386/tcg/translate.c > @@ -1686,27 +1686,27 @@ static void gen_shift_rm_T1(DisasContext *s, MemOp ot, int op1, > } > > tcg_gen_andi_tl(s->T1, s->T1, mask); > - tcg_gen_subi_tl(s->tmp0, s->T1, 1); > + tcg_gen_subi_tl(s->tmp4, s->T1, 1); > > if (is_right) { > if (is_arith) { > gen_exts(ot, s->T0); > - tcg_gen_sar_tl(s->tmp0, s->T0, s->tmp0); > + tcg_gen_sar_tl(s->tmp4, s->T0, s->tmp4); > tcg_gen_sar_tl(s->T0, s->T0, s->T1); > } else { > gen_extu(ot, s->T0); > - tcg_gen_shr_tl(s->tmp0, s->T0, s->tmp0); > + tcg_gen_shr_tl(s->tmp4, s->T0, s->tmp4); > tcg_gen_shr_tl(s->T0, s->T0, s->T1); > } > } else { > - tcg_gen_shl_tl(s->tmp0, s->T0, s->tmp0); > + tcg_gen_shl_tl(s->tmp4, s->T0, s->tmp4); > tcg_gen_shl_tl(s->T0, s->T0, s->T1); > } > > /* store */ > gen_op_st_rm_T0_A0(s, ot, op1); > > - gen_shift_flags(s, ot, s->T0, s->tmp0, s->T1, is_right); > + gen_shift_flags(s, ot, s->T0, s->tmp4, s->T1, is_right); > } The use of tmp0 vs tmp4 is completely local to this function. Within gen_shift_flags, the 4th argument is consistently used, and neither tmp0 nor tmp4 are referenced. If this does fix the issue, that means there's some other explanation, and possibly some deeper fix is required. r~