From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read
Date: Fri, 6 Nov 2020 15:20:29 +0100 [thread overview]
Message-ID: <1ef9a373-9c67-d12f-014a-9a88520b9635@amsat.org> (raw)
In-Reply-To: <68d4575deef2559b7a747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com>
On 11/6/20 3:32 AM, Alistair Francis wrote:
> After claiming the interrupt by reading the claim register we want to
> clear the register to make sure the interrupt doesn't appear at the next
> read.
>
> This matches the documentation for the claim register as it clears the
> pending bit (which we already do): https://docs.opentitan.org/hw/ip/rv_plic/doc/index.html
"When an interrupt is claimed by a target the relevant bit of IP is
cleared." Correct.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This also matches the current hardware.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> hw/intc/ibex_plic.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c
> index f49fa67c91..235e6b88ff 100644
> --- a/hw/intc/ibex_plic.c
> +++ b/hw/intc/ibex_plic.c
> @@ -139,6 +139,9 @@ static uint64_t ibex_plic_read(void *opaque, hwaddr addr,
> /* Return the current claimed interrupt */
> ret = s->claim;
>
> + /* Clear the claimed interrupt */
> + s->claim = 0x00000000;
> +
> /* Update the interrupt status after the claim */
> ibex_plic_update(s);
> }
>
next prev parent reply other threads:[~2020-11-06 14:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-06 2:32 [PATCH v1 1/1] hw/intc/ibex_plic: Clear the claim register when read Alistair Francis
2020-11-06 14:20 ` Philippe Mathieu-Daudé [this message]
2020-11-09 23:11 ` Alistair Francis
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