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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id d1-20020a05622a15c100b002f373d233d3sm5228803qty.71.2022.04.28.00.40.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Apr 2022 00:40:41 -0700 (PDT) Message-ID: <1f0cfaef-8b75-b13f-7713-d945cab6cbbb@redhat.com> Date: Thu, 28 Apr 2022 09:40:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH 1/2] hw/arm/smmuv3: Cache event fault record Content-Language: en-US To: Jean-Philippe Brucker References: <20220427111543.124620-1-jean-philippe@linaro.org> From: Eric Auger In-Reply-To: <20220427111543.124620-1-jean-philippe@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Jean, On 4/27/22 13:15, Jean-Philippe Brucker wrote: > The Record bit in the Context Descriptor tells the SMMU to report fault > events to the event queue. Since we don't cache the Record bit at the > moment, access faults from a cached Context Descriptor are never > reported. Store the Record bit in the cached SMMUTransCfg. Reviewed-by: Eric Auger Thanks! Eric > > Fixes: 9bde7f0674fe ("hw/arm/smmuv3: Implement translate callback") > Signed-off-by: Jean-Philippe Brucker > --- > hw/arm/smmuv3-internal.h | 1 - > include/hw/arm/smmu-common.h | 1 + > hw/arm/smmuv3.c | 14 +++++++------- > 3 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h > index d1885ae3f2..6de52bbf4d 100644 > --- a/hw/arm/smmuv3-internal.h > +++ b/hw/arm/smmuv3-internal.h > @@ -387,7 +387,6 @@ typedef struct SMMUEventInfo { > SMMUEventType type; > uint32_t sid; > bool recorded; > - bool record_trans_faults; > bool inval_ste_allowed; > union { > struct { > diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h > index 706be3c6d0..21e62342e9 100644 > --- a/include/hw/arm/smmu-common.h > +++ b/include/hw/arm/smmu-common.h > @@ -71,6 +71,7 @@ typedef struct SMMUTransCfg { > bool disabled; /* smmu is disabled */ > bool bypassed; /* translation is bypassed */ > bool aborted; /* translation is aborted */ > + bool record_faults; /* record fault events */ > uint64_t ttb; /* TT base address */ > uint8_t oas; /* output address width */ > uint8_t tbi; /* Top Byte Ignore */ > diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c > index 707eb430c2..8b1d8103dc 100644 > --- a/hw/arm/smmuv3.c > +++ b/hw/arm/smmuv3.c > @@ -527,7 +527,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) > trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz, tt->had); > } > > - event->record_trans_faults = CD_R(cd); > + cfg->record_faults = CD_R(cd); > > return 0; > > @@ -680,7 +680,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > > tt = select_tt(cfg, addr); > if (!tt) { > - if (event.record_trans_faults) { > + if (cfg->record_faults) { > event.type = SMMU_EVT_F_TRANSLATION; > event.u.f_translation.addr = addr; > event.u.f_translation.rnw = flag & 0x1; > @@ -696,7 +696,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > if (cached_entry) { > if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) { > status = SMMU_TRANS_ERROR; > - if (event.record_trans_faults) { > + if (cfg->record_faults) { > event.type = SMMU_EVT_F_PERMISSION; > event.u.f_permission.addr = addr; > event.u.f_permission.rnw = flag & 0x1; > @@ -720,28 +720,28 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr, > event.u.f_walk_eabt.addr2 = ptw_info.addr; > break; > case SMMU_PTW_ERR_TRANSLATION: > - if (event.record_trans_faults) { > + if (cfg->record_faults) { > event.type = SMMU_EVT_F_TRANSLATION; > event.u.f_translation.addr = addr; > event.u.f_translation.rnw = flag & 0x1; > } > break; > case SMMU_PTW_ERR_ADDR_SIZE: > - if (event.record_trans_faults) { > + if (cfg->record_faults) { > event.type = SMMU_EVT_F_ADDR_SIZE; > event.u.f_addr_size.addr = addr; > event.u.f_addr_size.rnw = flag & 0x1; > } > break; > case SMMU_PTW_ERR_ACCESS: > - if (event.record_trans_faults) { > + if (cfg->record_faults) { > event.type = SMMU_EVT_F_ACCESS; > event.u.f_access.addr = addr; > event.u.f_access.rnw = flag & 0x1; > } > break; > case SMMU_PTW_ERR_PERMISSION: > - if (event.record_trans_faults) { > + if (cfg->record_faults) { > event.type = SMMU_EVT_F_PERMISSION; > event.u.f_permission.addr = addr; > event.u.f_permission.rnw = flag & 0x1;