* [PATCH] hw/riscv/virt: Add a second UART for secure world
@ 2023-04-24 1:01 Yong Li
2023-04-24 2:42 ` LIU Zhiwei
2023-04-24 15:21 ` Philippe Mathieu-Daudé
0 siblings, 2 replies; 8+ messages in thread
From: Yong Li @ 2023-04-24 1:01 UTC (permalink / raw)
To: qemu-devel; +Cc: Yong Li, Zhiwei Liu
The virt machine can have two UARTs and the second UART
can be used when host secure-mode support is enabled.
Signed-off-by: Yong Li <yong.li@intel.com>
Cc: "Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
---
hw/riscv/virt.c | 4 ++++
include/hw/riscv/virt.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b38b41e685..02475e1678 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
+ [VIRT_UART1] = { 0x10002000, 0x100 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
@@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ serial_mm_init(system_memory, memmap[VIRT_UART1].base,
+ 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
+ serial_hd(1), DEVICE_LITTLE_ENDIAN);
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..8d2f8f225d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -74,6 +74,7 @@ enum {
VIRT_APLIC_S,
VIRT_UART0,
VIRT_VIRTIO,
+ VIRT_UART1,
VIRT_FW_CFG,
VIRT_IMSIC_M,
VIRT_IMSIC_S,
@@ -88,6 +89,7 @@ enum {
enum {
UART0_IRQ = 10,
RTC_IRQ = 11,
+ UART1_IRQ = 12,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv/virt: Add a second UART for secure world
2023-04-24 1:01 Yong Li
@ 2023-04-24 2:42 ` LIU Zhiwei
2023-04-24 5:50 ` Li, Yong
2023-04-24 15:21 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 8+ messages in thread
From: LIU Zhiwei @ 2023-04-24 2:42 UTC (permalink / raw)
To: Yong Li, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2410 bytes --]
On 2023/4/24 9:01, Yong Li wrote:
> The virt machine can have two UARTs and the second UART
> can be used when host secure-mode support is enabled.
>
> Signed-off-by: Yong Li<yong.li@intel.com>
> Cc: "Zhiwei Liu"<zhiwei_liu@linux.alibaba.com>
Should cc other Maintainers and Reviewers. Get the list by running the
script
./scripts/get_maintainer.pl yours.patch
> ---
> hw/riscv/virt.c | 4 ++++
> include/hw/riscv/virt.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index b38b41e685..02475e1678 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
> [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
> [VIRT_UART0] = { 0x10000000, 0x100 },
> [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
> + [VIRT_UART1] = { 0x10002000, 0x100 },
Can we move it a position adjacent to the VIRT_UART0, such as 0x10000100?
Otherwise,
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Zhiwei
> [VIRT_FW_CFG] = { 0x10100000, 0x18 },
> [VIRT_FLASH] = { 0x20000000, 0x4000000 },
> [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
> @@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + serial_mm_init(system_memory, memmap[VIRT_UART1].base,
> + 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
> + serial_hd(1), DEVICE_LITTLE_ENDIAN);
>
> sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
> qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index e5c474b26e..8d2f8f225d 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -74,6 +74,7 @@ enum {
> VIRT_APLIC_S,
> VIRT_UART0,
> VIRT_VIRTIO,
> + VIRT_UART1,
> VIRT_FW_CFG,
> VIRT_IMSIC_M,
> VIRT_IMSIC_S,
> @@ -88,6 +89,7 @@ enum {
> enum {
> UART0_IRQ = 10,
> RTC_IRQ = 11,
> + UART1_IRQ = 12,
> VIRTIO_IRQ = 1, /* 1 to 8 */
> VIRTIO_COUNT = 8,
> PCIE_IRQ = 0x20, /* 32 to 35 */
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* Re: [PATCH] hw/riscv/virt: Add a second UART for secure world
2023-04-24 2:42 ` LIU Zhiwei
@ 2023-04-24 5:50 ` Li, Yong
0 siblings, 0 replies; 8+ messages in thread
From: Li, Yong @ 2023-04-24 5:50 UTC (permalink / raw)
To: LIU Zhiwei, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2770 bytes --]
On 2023/4/24 10:42, LIU Zhiwei wrote:
>
>
> On 2023/4/24 9:01, Yong Li wrote:
>> The virt machine can have two UARTs and the second UART
>> can be used when host secure-mode support is enabled.
>>
>> Signed-off-by: Yong Li<yong.li@intel.com>
>> Cc: "Zhiwei Liu"<zhiwei_liu@linux.alibaba.com>
>
> Should cc other Maintainers and Reviewers. Get the list by running
> the script
>
> ./scripts/get_maintainer.pl yours.patch
>
Sure,
>> ---
>> hw/riscv/virt.c | 4 ++++
>> include/hw/riscv/virt.h | 2 ++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
>> index b38b41e685..02475e1678 100644
>> --- a/hw/riscv/virt.c
>> +++ b/hw/riscv/virt.c
>> @@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
>> [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
>> [VIRT_UART0] = { 0x10000000, 0x100 },
>> [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
>> + [VIRT_UART1] = { 0x10002000, 0x100 },
>
> Can we move it a position adjacent to the VIRT_UART0, such as 0x10000100?
>
> Otherwise,
>
This probably cause back compatible issue to the firmware or other code
who use VIRT_VIRTIO.
Actually, similar code in hw/arm/sbsa-ref.c, the UART devices' address
are also not continuously.
It should not be a problem. Thanks!
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
>
> Zhiwei
>
>> [VIRT_FW_CFG] = { 0x10100000, 0x18 },
>> [VIRT_FLASH] = { 0x20000000, 0x4000000 },
>> [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
>> @@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
>> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
>> 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
>> serial_hd(0), DEVICE_LITTLE_ENDIAN);
>> + serial_mm_init(system_memory, memmap[VIRT_UART1].base,
>> + 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
>> + serial_hd(1), DEVICE_LITTLE_ENDIAN);
>>
>> sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
>> qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
>> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
>> index e5c474b26e..8d2f8f225d 100644
>> --- a/include/hw/riscv/virt.h
>> +++ b/include/hw/riscv/virt.h
>> @@ -74,6 +74,7 @@ enum {
>> VIRT_APLIC_S,
>> VIRT_UART0,
>> VIRT_VIRTIO,
>> + VIRT_UART1,
>> VIRT_FW_CFG,
>> VIRT_IMSIC_M,
>> VIRT_IMSIC_S,
>> @@ -88,6 +89,7 @@ enum {
>> enum {
>> UART0_IRQ = 10,
>> RTC_IRQ = 11,
>> + UART1_IRQ = 12,
>> VIRTIO_IRQ = 1, /* 1 to 8 */
>> VIRTIO_COUNT = 8,
>> PCIE_IRQ = 0x20, /* 32 to 35 */
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] hw/riscv/virt: Add a second UART for secure world
@ 2023-04-24 6:24 Yong Li
2023-04-24 8:59 ` Peter Maydell
0 siblings, 1 reply; 8+ messages in thread
From: Yong Li @ 2023-04-24 6:24 UTC (permalink / raw)
To: qemu-devel
Cc: Yong Li, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
The virt machine can have two UARTs and the second UART
can be used when host secure-mode support is enabled.
Signed-off-by: Yong Li <yong.li@intel.com>
---
hw/riscv/virt.c | 4 ++++
include/hw/riscv/virt.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b38b41e685..02475e1678 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
+ [VIRT_UART1] = { 0x10002000, 0x100 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
@@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ serial_mm_init(system_memory, memmap[VIRT_UART1].base,
+ 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
+ serial_hd(1), DEVICE_LITTLE_ENDIAN);
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..8d2f8f225d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -74,6 +74,7 @@ enum {
VIRT_APLIC_S,
VIRT_UART0,
VIRT_VIRTIO,
+ VIRT_UART1,
VIRT_FW_CFG,
VIRT_IMSIC_M,
VIRT_IMSIC_S,
@@ -88,6 +89,7 @@ enum {
enum {
UART0_IRQ = 10,
RTC_IRQ = 11,
+ UART1_IRQ = 12,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv/virt: Add a second UART for secure world
2023-04-24 6:24 [PATCH] hw/riscv/virt: Add a second UART for secure world Yong Li
@ 2023-04-24 8:59 ` Peter Maydell
2023-04-24 10:43 ` Li, Yong
0 siblings, 1 reply; 8+ messages in thread
From: Peter Maydell @ 2023-04-24 8:59 UTC (permalink / raw)
To: Yong Li
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
On Mon, 24 Apr 2023 at 07:24, Yong Li <yong.li@intel.com> wrote:
>
> The virt machine can have two UARTs and the second UART
> can be used when host secure-mode support is enabled.
Do you mean "host" here, or "guest" ?
> Signed-off-by: Yong Li <yong.li@intel.com>
> ---
> hw/riscv/virt.c | 4 ++++
> include/hw/riscv/virt.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index b38b41e685..02475e1678 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
> [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
> [VIRT_UART0] = { 0x10000000, 0x100 },
> [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
> + [VIRT_UART1] = { 0x10002000, 0x100 },
> [VIRT_FW_CFG] = { 0x10100000, 0x18 },
> [VIRT_FLASH] = { 0x20000000, 0x4000000 },
> [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
> @@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
> 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
> serial_hd(0), DEVICE_LITTLE_ENDIAN);
> + serial_mm_init(system_memory, memmap[VIRT_UART1].base,
> + 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
> + serial_hd(1), DEVICE_LITTLE_ENDIAN);
>
> sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
> qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
Is it intentional that you only create the UART device
and do not add it to the FDT ? (UART0 doesn't seem to be
in the ACPI table generation code so I guess that part
is OK.)
You probably also want to test for compatibility:
for arm we found that different bits of software
(firmware, Linux kernel) annoyingly iterated through
the dtb in different orders.
thanks
-- PMM
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv/virt: Add a second UART for secure world
2023-04-24 8:59 ` Peter Maydell
@ 2023-04-24 10:43 ` Li, Yong
0 siblings, 0 replies; 8+ messages in thread
From: Li, Yong @ 2023-04-24 10:43 UTC (permalink / raw)
To: Peter Maydell
Cc: qemu-devel, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
[-- Attachment #1: Type: text/plain, Size: 2341 bytes --]
On 2023/4/24 16:59, Peter Maydell wrote:
> On Mon, 24 Apr 2023 at 07:24, Yong Li<yong.li@intel.com> wrote:
>> The virt machine can have two UARTs and the second UART
>> can be used when host secure-mode support is enabled.
> Do you mean "host" here, or "guest" ?
Currently, it is an UEFI secure firmware residing in a secure
partition. Let me update the message with a v2 patch
>> Signed-off-by: Yong Li<yong.li@intel.com>
>> ---
>> hw/riscv/virt.c | 4 ++++
>> include/hw/riscv/virt.h | 2 ++
>> 2 files changed, 6 insertions(+)
>>
>> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
>> index b38b41e685..02475e1678 100644
>> --- a/hw/riscv/virt.c
>> +++ b/hw/riscv/virt.c
>> @@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
>> [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
>> [VIRT_UART0] = { 0x10000000, 0x100 },
>> [VIRT_VIRTIO] = { 0x10001000, 0x1000 },
>> + [VIRT_UART1] = { 0x10002000, 0x100 },
>> [VIRT_FW_CFG] = { 0x10100000, 0x18 },
>> [VIRT_FLASH] = { 0x20000000, 0x4000000 },
>> [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
>> @@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
>> serial_mm_init(system_memory, memmap[VIRT_UART0].base,
>> 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
>> serial_hd(0), DEVICE_LITTLE_ENDIAN);
>> + serial_mm_init(system_memory, memmap[VIRT_UART1].base,
>> + 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
>> + serial_hd(1), DEVICE_LITTLE_ENDIAN);
>>
>> sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
>> qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
> Is it intentional that you only create the UART device
> and do not add it to the FDT ? (UART0 doesn't seem to be
> in the ACPI table generation code so I guess that part
> is OK.)
>
> You probably also want to test for compatibility:
> for arm we found that different bits of software
> (firmware, Linux kernel) annoyingly iterated through
> the dtb in different orders.
Thanks for the comments.
Yes, tested with our software stack which has edk2 , u-boot firmware,
and also linux/debian os. No compatibility issue.
>
> thanks
> -- PMM
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] hw/riscv/virt: Add a second UART for secure world
@ 2023-04-24 10:51 Yong Li
0 siblings, 0 replies; 8+ messages in thread
From: Yong Li @ 2023-04-24 10:51 UTC (permalink / raw)
To: qemu-devel
Cc: Yong Li, Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, open list:RISC-V TCG CPUs
The virt machine can have two UARTs and the second UART
can be used when host secure-mode support is enabled.
Signed-off-by: Yong Li <yong.li@intel.com>
---
hw/riscv/virt.c | 4 ++++
include/hw/riscv/virt.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index b38b41e685..02475e1678 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -88,6 +88,7 @@ static const MemMapEntry virt_memmap[] = {
[VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) },
[VIRT_UART0] = { 0x10000000, 0x100 },
[VIRT_VIRTIO] = { 0x10001000, 0x1000 },
+ [VIRT_UART1] = { 0x10002000, 0x100 },
[VIRT_FW_CFG] = { 0x10100000, 0x18 },
[VIRT_FLASH] = { 0x20000000, 0x4000000 },
[VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE },
@@ -1508,6 +1509,9 @@ static void virt_machine_init(MachineState *machine)
serial_mm_init(system_memory, memmap[VIRT_UART0].base,
0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193,
serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ serial_mm_init(system_memory, memmap[VIRT_UART1].base,
+ 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART1_IRQ), 399193,
+ serial_hd(1), DEVICE_LITTLE_ENDIAN);
sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ));
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index e5c474b26e..8d2f8f225d 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -74,6 +74,7 @@ enum {
VIRT_APLIC_S,
VIRT_UART0,
VIRT_VIRTIO,
+ VIRT_UART1,
VIRT_FW_CFG,
VIRT_IMSIC_M,
VIRT_IMSIC_S,
@@ -88,6 +89,7 @@ enum {
enum {
UART0_IRQ = 10,
RTC_IRQ = 11,
+ UART1_IRQ = 12,
VIRTIO_IRQ = 1, /* 1 to 8 */
VIRTIO_COUNT = 8,
PCIE_IRQ = 0x20, /* 32 to 35 */
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] hw/riscv/virt: Add a second UART for secure world
2023-04-24 1:01 Yong Li
2023-04-24 2:42 ` LIU Zhiwei
@ 2023-04-24 15:21 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 8+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-04-24 15:21 UTC (permalink / raw)
To: Yong Li, qemu-devel; +Cc: Zhiwei Liu
On 24/4/23 03:01, Yong Li wrote:
> The virt machine can have two UARTs and the second UART
> can be used when host secure-mode support is enabled.
>
> Signed-off-by: Yong Li <yong.li@intel.com>
> Cc: "Zhiwei Liu" <zhiwei_liu@linux.alibaba.com>
> ---
> hw/riscv/virt.c | 4 ++++
> include/hw/riscv/virt.h | 2 ++
> 2 files changed, 6 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-04-24 16:31 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2023-04-24 6:24 [PATCH] hw/riscv/virt: Add a second UART for secure world Yong Li
2023-04-24 8:59 ` Peter Maydell
2023-04-24 10:43 ` Li, Yong
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2023-04-24 10:51 Yong Li
2023-04-24 1:01 Yong Li
2023-04-24 2:42 ` LIU Zhiwei
2023-04-24 5:50 ` Li, Yong
2023-04-24 15:21 ` Philippe Mathieu-Daudé
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