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Tue, 06 Feb 2024 22:02:03 -0800 (PST) Message-ID: <1f483920-b99d-4d5c-9f9a-423f79986c23@linaro.org> Date: Wed, 7 Feb 2024 10:01:58 +0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/17] plugins: implement inline operation relative to cpu_index Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: Eduardo Habkost , Alexandre Iooss , =?UTF-8?Q?Alex_Benn=C3=A9e?= , Mahmoud Mandour , Marcel Apfelbaum , Yanan Wang , Paolo Bonzini , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= References: <20240206092423.3005995-1-pierrick.bouvier@linaro.org> <20240206092423.3005995-8-pierrick.bouvier@linaro.org> <1838c7f7-db41-4328-b75b-6b392f600bd2@linaro.org> From: Pierrick Bouvier In-Reply-To: <1838c7f7-db41-4328-b75b-6b392f600bd2@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/7/24 07:42, Richard Henderson wrote: > On 2/6/24 19:24, Pierrick Bouvier wrote: >> Instead of working on a fixed memory location, allow to address it based >> on cpu_index, an element size and a given offset. >> Result address: ptr + offset + cpu_index * element_size. >> >> With this, we can target a member in a struct array from a base pointer. >> >> Current semantic is not modified, thus inline operation still targets >> always the same memory location. >> >> Signed-off-by: Pierrick Bouvier >> --- >> plugins/plugin.h | 2 +- >> accel/tcg/plugin-gen.c | 65 +++++++++++++++++++++++++++++++++++------- >> plugins/api.c | 3 +- >> plugins/core.c | 12 +++++--- >> 4 files changed, 65 insertions(+), 17 deletions(-) >> >> diff --git a/plugins/plugin.h b/plugins/plugin.h >> index fd93a372803..77ed10689ca 100644 >> --- a/plugins/plugin.h >> +++ b/plugins/plugin.h >> @@ -100,7 +100,7 @@ void plugin_register_vcpu_mem_cb(GArray **arr, >> enum qemu_plugin_mem_rw rw, >> void *udata); >> >> -void exec_inline_op(struct qemu_plugin_dyn_cb *cb); >> +void exec_inline_op(struct qemu_plugin_dyn_cb *cb, int cpu_index); >> >> int plugin_num_vcpus(void); >> >> diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c >> index b37ce7683e6..68dee4c68d3 100644 >> --- a/accel/tcg/plugin-gen.c >> +++ b/accel/tcg/plugin-gen.c >> @@ -132,16 +132,28 @@ static void gen_empty_udata_cb_no_rwg(void) >> */ >> static void gen_empty_inline_cb(void) >> { >> + TCGv_i32 cpu_index = tcg_temp_ebb_new_i32(); >> + TCGv_ptr cpu_index_as_ptr = tcg_temp_ebb_new_ptr(); >> TCGv_i64 val = tcg_temp_ebb_new_i64(); >> TCGv_ptr ptr = tcg_temp_ebb_new_ptr(); >> >> + tcg_gen_ld_i32(cpu_index, tcg_env, >> + -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); >> + /* pass an immediate != 0 so that it doesn't get optimized away */ >> + tcg_gen_muli_i32(cpu_index, cpu_index, 0xdeadbeef); > > You don't need a random immediate here. > You can just as easily use > > tcg_gen_mul_i32(cpu_index, cpu_index, cpu_index); > > with a similar comment about the true size being inserted later. > Followed the tcg_gen_addi_i64 that was using this pattern in the same file. I'll change this to what you recommend. > Otherwise, > Reviewed-by: Richard Henderson > > > r~