From: Richard Henderson <richard.henderson@linaro.org>
To: Furquan Shaikh <furquan@rivosinc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] riscv: Make semihosting configurable for all privilege modes
Date: Fri, 12 Aug 2022 19:31:59 -0700 [thread overview]
Message-ID: <1f4b1b9b-51a0-8970-83ed-b4618a60cb1a@linaro.org> (raw)
In-Reply-To: <CA+tJHD6gNrtcrZ9bkDet8NuiR8mcSQfeN-Rk3dtm3LmeakKnvQ@mail.gmail.com>
On 8/12/22 17:50, Furquan Shaikh wrote:
>> Why do you need such fine-grained control? What is the use-case?
>
> I ran into a problem when I was testing a project (with a microkernel
> in M-mode and tasks in U-mode) that uses semihosting for debugging.
> The semihosting worked fine for M-mode but not in U-mode.
Sure. This would be handled by Peter's proposed userspace-enable=on property.
> As I started
> digging into this, I realized that this is because qemu restricts
> semihosting to only M and S modes. From reading the debug spec, I
> understood that the DCSR presents options for ebreak behavior in each
> mode including VS and VU.
I strongly suspect that VS also already works, since that's just
env->priv == PRV_S && riscv_cpu_virt_enabled(env)
VU would also be handled by userspace-enable=on.
I do not see any use for 5 separate properties.
r~
next prev parent reply other threads:[~2022-08-13 2:33 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-11 20:41 [PATCH] riscv: Make semihosting configurable for all privilege modes Furquan Shaikh
2022-08-11 20:56 ` Furquan Shaikh
2022-08-11 23:27 ` Philippe Mathieu-Daudé via
2022-08-12 11:04 ` Andrew Jones
2022-08-12 22:05 ` Furquan Shaikh
2022-08-12 23:00 ` Palmer Dabbelt
2022-08-12 23:28 ` Furquan Shaikh
2022-08-12 11:28 ` Peter Maydell
2022-08-12 23:11 ` Furquan Shaikh
2022-08-12 23:27 ` Richard Henderson
2022-08-12 23:42 ` Richard Henderson
2022-08-12 23:57 ` Furquan Shaikh
2022-08-13 0:30 ` Richard Henderson
2022-08-13 0:50 ` Furquan Shaikh
2022-08-13 2:31 ` Richard Henderson [this message]
2022-08-13 5:22 ` Furquan Shaikh
2022-08-13 10:19 ` Peter Maydell
2022-08-14 22:03 ` Alistair Francis
2022-08-15 6:24 ` Furquan Shaikh
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