From: Richard Henderson <richard.henderson@linaro.org>
To: Jiajie Chen <c@jia.je>, qemu-devel@nongnu.org
Cc: gaosong@loongson.cn, git@xen0n.name
Subject: Re: [PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt
Date: Fri, 1 Sep 2023 10:24:39 -0700 [thread overview]
Message-ID: <1f963ece-d5b6-50c7-5e40-bc04867494f7@linaro.org> (raw)
In-Reply-To: <20230901093258.942357-4-c@jia.je>
On 9/1/23 02:30, Jiajie Chen wrote:
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> tcg/loongarch64/tcg-target-con-set.h | 1 +
> tcg/loongarch64/tcg-target.c.inc | 60 ++++++++++++++++++++++++++++
> 2 files changed, 61 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h
> index 37b3f80bf9..d04916db25 100644
> --- a/tcg/loongarch64/tcg-target-con-set.h
> +++ b/tcg/loongarch64/tcg-target-con-set.h
> @@ -31,4 +31,5 @@ C_O1_I2(r, 0, rZ)
> C_O1_I2(r, rZ, ri)
> C_O1_I2(r, rZ, rJ)
> C_O1_I2(r, rZ, rZ)
> +C_O1_I2(w, w, wJ)
Notes for improvement: 'J' is a signed 32-bit immediate.
> + if (const_args[2]) {
> + /*
> + * cmp_vec dest, src, value
> + * Try vseqi/vslei/vslti
> + */
> + int64_t value = sextract64(a2, 0, 8 << vece);
> + if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \
> + cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) {
> + tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \
> + a0, a1, value));
> + break;
> + } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) &&
> + (0x00 <= value && value <= 0x1f)) {
> + tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \
> + a0, a1, value));
Better would be a new constraint that only matches
-0x10 <= x <= 0x1f
If the sign is wrong for the comparison, it can *always* be loaded with just vldi.
Whereas at present, using J,
> + tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
> + a2 = temp_vec;
this may require 3 instructions (lu12i.w + ori + vreplgr2vr).
By constraining the constants allowed, you allow the register allocator to see that a
register is required, which may be reused for another instruction.
r~
next prev parent reply other threads:[~2023-09-01 17:25 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-01 9:30 [PATCH v2 00/14] Lower TCG vector ops to LSX Jiajie Chen
2023-09-01 9:30 ` [PATCH v2 01/14] tcg/loongarch64: Import LSX instructions Jiajie Chen
2023-09-01 17:06 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 02/14] tcg/loongarch64: Lower basic tcg vec ops to LSX Jiajie Chen
2023-09-01 17:05 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 03/14] tcg/loongarch64: Lower cmp_vec to vseq/vsle/vslt Jiajie Chen
2023-09-01 17:24 ` Richard Henderson [this message]
2023-09-01 17:28 ` Jiajie Chen
2023-09-01 17:48 ` Richard Henderson
2023-09-02 1:06 ` Jiajie Chen
2023-09-01 9:30 ` [PATCH v2 04/14] tcg/loongarch64: Lower add/sub_vec to vadd/vsub Jiajie Chen
2023-09-01 17:58 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 05/14] tcg/loongarch64: Lower vector bitwise operations Jiajie Chen
2023-09-01 17:59 ` Richard Henderson
2023-09-01 9:30 ` [PATCH v2 06/14] tcg/loongarch64: Lower neg_vec to vneg Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 07/14] tcg/loongarch64: Lower mul_vec to vmul Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 08/14] tcg/loongarch64: Lower vector min max ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 09/14] tcg/loongarch64: Lower vector saturated ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 10/14] tcg/loongarch64: Lower vector shift vector ops Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 11/14] tcg/loongarch64: Lower bitsel_vec to vbitsel Jiajie Chen
2023-09-01 9:31 ` [PATCH v2 12/14] tcg/loongarch64: Lower vector shift integer ops Jiajie Chen
2023-09-01 18:01 ` Richard Henderson
2023-09-01 9:31 ` [PATCH v2 13/14] tcg/loongarch64: Lower rotv_vec ops to LSX Jiajie Chen
2023-09-01 18:02 ` Richard Henderson
2023-09-01 9:31 ` [PATCH v2 14/14] tcg/loongarch64: Lower rotli_vec to vrotri Jiajie Chen
2023-09-01 18:06 ` Richard Henderson
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