From: Harsh Prateek Bora <harshpb@linux.ibm.com>
To: Nicholas Piggin <npiggin@gmail.com>, qemu-ppc@nongnu.org
Cc: "Caleb Schlossin" <calebs@linux.vnet.ibm.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
qemu-devel@nongnu.org
Subject: Re: [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads
Date: Tue, 28 May 2024 14:46:40 +0530 [thread overview]
Message-ID: <1f9c8eb6-aa4f-4740-89a6-20b510b21d7d@linux.ibm.com> (raw)
In-Reply-To: <20240526122612.473476-8-npiggin@gmail.com>
On 5/26/24 17:56, Nicholas Piggin wrote:
> Add helpers for TCG code to determine if there are SMT siblings
> sharing per-core and per-lpar registers. This simplifies the
> callers and makes SMT register topology simpler to modify with
> later changes.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/cpu.h | 7 +++++++
> target/ppc/cpu_init.c | 2 +-
> target/ppc/excp_helper.c | 16 +++++++---------
> target/ppc/misc_helper.c | 27 ++++++---------------------
> target/ppc/timebase_helper.c | 20 +++++++-------------
> 5 files changed, 28 insertions(+), 44 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 9a89083932..8fd6ade471 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1406,6 +1406,13 @@ struct CPUArchState {
> uint64_t pmu_base_time;
> };
>
> +#define PPC_CPU_HAS_CORE_SIBLINGS(cs) \
> + (cs->nr_threads > 1)
> +
> +#define PPC_CPU_HAS_LPAR_SIBLINGS(cs) \
> + ((POWERPC_CPU(cs)->env.flags & POWERPC_FLAG_SMT_1LPAR) && \
> + PPC_CPU_HAS_CORE_SIBLINGS(cs))
> +
> #define _CORE_ID(cs) \
> (POWERPC_CPU(cs)->env.core_index)
>
> diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
> index ae483e20c4..e71ee008ed 100644
> --- a/target/ppc/cpu_init.c
> +++ b/target/ppc/cpu_init.c
> @@ -6975,7 +6975,7 @@ static void ppc_cpu_realize(DeviceState *dev, Error **errp)
>
> pcc->parent_realize(dev, errp);
>
> - if (env_cpu(env)->nr_threads > 1) {
> + if (PPC_CPU_HAS_CORE_SIBLINGS(cs)) {
> env->flags |= POWERPC_FLAG_SMT;
> }
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 0cd542675f..fd45da0f2b 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -3029,7 +3029,7 @@ void helper_book3s_msgsnd(CPUPPCState *env, target_ulong rb)
> brdcast = true;
> }
>
> - if (cs->nr_threads == 1 || !brdcast) {
> + if (!PPC_CPU_HAS_CORE_SIBLINGS(cs) || !brdcast) {
Since there are multiple usage of above macro in negation below as well,
we may probably want to introduce another macro PPC_CPU_HAS_SINGLE_CORE
which checks only for nr_threads == 1. Anyways,
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
> ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1);
> return;
> }
> @@ -3067,21 +3067,19 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb)
> CPUState *cs = env_cpu(env);
> PowerPCCPU *cpu = env_archcpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
> int ttir = rb & PPC_BITMASK(57, 63);
>
> helper_hfscr_facility_check(env, HFSCR_MSGP, "msgsndp", HFSCR_IC_MSGP);
>
> - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> - nr_threads = 1; /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
> - }
> -
> - if (!dbell_type_server(rb) || ttir >= nr_threads) {
> + if (!dbell_type_server(rb)) {
> return;
> }
>
> - if (nr_threads == 1) {
> - ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, 1);
> + /* msgsndp behaves as 1-thread in LPAR-per-thread mode*/
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> + if (ttir == 0) {
> + ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, 1);
> + }
> return;
> }
>
> diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
> index 46ba3a5584..598c956cdd 100644
> --- a/target/ppc/misc_helper.c
> +++ b/target/ppc/misc_helper.c
> @@ -49,9 +49,8 @@ void helper_spr_core_write_generic(CPUPPCState *env, uint32_t sprn,
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1) {
> + if (!PPC_CPU_HAS_CORE_SIBLINGS(cs)) {
> env->spr[sprn] = val;
> return;
> }
> @@ -196,7 +195,7 @@ void helper_store_ptcr(CPUPPCState *env, target_ulong val)
> return;
> }
>
> - if (cs->nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> env->spr[SPR_PTCR] = val;
> tlb_flush(cs);
> } else {
> @@ -243,16 +242,12 @@ target_ulong helper_load_dpdes(CPUPPCState *env)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
> target_ulong dpdes = 0;
>
> helper_hfscr_facility_check(env, HFSCR_MSGP, "load DPDES", HFSCR_IC_MSGP);
>
> - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> - nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
> - }
> -
> - if (nr_threads == 1) {
> + /* DPDES behaves as 1-thread in LPAR-per-thread mode */
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
> dpdes = 1;
> }
> @@ -279,21 +274,11 @@ void helper_store_dpdes(CPUPPCState *env, target_ulong val)
> PowerPCCPU *cpu = env_archcpu(env);
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> helper_hfscr_facility_check(env, HFSCR_MSGP, "store DPDES", HFSCR_IC_MSGP);
>
> - if (!(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> - nr_threads = 1; /* DPDES behaves as 1-thread in LPAR-per-thread mode */
> - }
> -
> - if (val & ~(nr_threads - 1)) {
> - qemu_log_mask(LOG_GUEST_ERROR, "Invalid DPDES register value "
> - TARGET_FMT_lx"\n", val);
> - val &= (nr_threads - 1); /* Ignore the invalid bits */
> - }
> -
> - if (nr_threads == 1) {
> + /* DPDES behaves as 1-thread in LPAR-per-thread mode */
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> ppc_set_irq(cpu, PPC_INTERRUPT_DOORBELL, val & 0x1);
> return;
> }
> diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c
> index 788c498d63..abe7b95696 100644
> --- a/target/ppc/timebase_helper.c
> +++ b/target/ppc/timebase_helper.c
> @@ -63,9 +63,8 @@ void helper_store_purr(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> cpu_ppc_store_purr(env, val);
> return;
> }
> @@ -82,9 +81,8 @@ void helper_store_tbl(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> cpu_ppc_store_tbl(env, val);
> return;
> }
> @@ -99,9 +97,8 @@ void helper_store_tbu(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> cpu_ppc_store_tbu(env, val);
> return;
> }
> @@ -141,9 +138,8 @@ void helper_store_hdecr(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> cpu_ppc_store_hdecr(env, val);
> return;
> }
> @@ -158,9 +154,8 @@ void helper_store_vtb(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> cpu_ppc_store_vtb(env, val);
> return;
> }
> @@ -175,9 +170,8 @@ void helper_store_tbu40(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
> CPUState *ccs;
> - uint32_t nr_threads = cs->nr_threads;
>
> - if (nr_threads == 1 || !(env->flags & POWERPC_FLAG_SMT_1LPAR)) {
> + if (!PPC_CPU_HAS_LPAR_SIBLINGS(cs)) {
> cpu_ppc_store_tbu40(env, val);
> return;
> }
> @@ -288,7 +282,7 @@ static void write_tfmr(CPUPPCState *env, target_ulong val)
> {
> CPUState *cs = env_cpu(env);
>
> - if (cs->nr_threads == 1) {
> + if (!PPC_CPU_HAS_CORE_SIBLINGS(cs)) {
> env->spr[SPR_TFMR] = val;
> } else {
> CPUState *ccs;
next prev parent reply other threads:[~2024-05-28 9:17 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-26 12:26 [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 01/10] ppc/pnv: Add pointer from PnvCPUState to PnvCore Nicholas Piggin
2024-05-27 15:23 ` Cédric Le Goater
2024-05-28 6:19 ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 02/10] ppc/pnv: Move timebase state into PnvCore Nicholas Piggin
2024-05-28 6:28 ` Harsh Prateek Bora
2024-05-28 7:52 ` Cédric Le Goater
2024-05-29 0:19 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 03/10] target/ppc: Improve SPR indirect registers Nicholas Piggin
2024-05-28 6:50 ` Harsh Prateek Bora
2024-05-29 0:13 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 04/10] ppc/pnv: specialise init for powernv8/9/10 machines Nicholas Piggin
2024-05-28 7:10 ` Harsh Prateek Bora
2024-05-28 7:45 ` Cédric Le Goater
2024-05-29 0:18 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 05/10] ppc/pnv: Extend chip_pir class method to TIR as well Nicholas Piggin
2024-05-28 8:32 ` Harsh Prateek Bora
2024-05-29 0:24 ` Nicholas Piggin
2024-05-29 6:30 ` Cédric Le Goater
2024-05-30 6:38 ` Nicholas Piggin
2024-05-30 6:42 ` Cédric Le Goater
2024-05-26 12:26 ` [RFC PATCH 06/10] ppc: Add a core_index to CPUPPCState for SMT vCPUs Nicholas Piggin
2024-05-28 8:48 ` Harsh Prateek Bora
2024-05-28 8:52 ` Harsh Prateek Bora
2024-05-29 0:28 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 07/10] target/ppc: Add helpers to check for SMT sibling threads Nicholas Piggin
2024-05-28 9:16 ` Harsh Prateek Bora [this message]
2024-05-29 0:31 ` Nicholas Piggin
2024-05-29 6:34 ` Cédric Le Goater
2024-05-30 6:38 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 08/10] ppc/pnv: Invert the design for big-core machine modelling Nicholas Piggin
2024-05-29 6:57 ` Cédric Le Goater
2024-05-30 6:52 ` Nicholas Piggin
2024-05-30 7:46 ` Cédric Le Goater
2024-06-03 5:22 ` Nicholas Piggin
2024-05-29 10:49 ` Harsh Prateek Bora
2024-05-26 12:26 ` [RFC PATCH 09/10] ppc/pnv: Implement POWER10 PC xscom registers for direct controls Nicholas Piggin
2024-05-29 7:00 ` Cédric Le Goater
2024-05-30 6:53 ` Nicholas Piggin
2024-05-26 12:26 ` [RFC PATCH 10/10] ppc/pnv: Add an LPAR per core machine option Nicholas Piggin
2024-05-29 7:02 ` Cédric Le Goater
2024-05-27 6:25 ` [RFC PATCH 00/10] ppc/pnv: Better big-core model, lpar-per-core, PC unit Cédric Le Goater
2024-05-27 7:32 ` Nicholas Piggin
2024-05-27 7:36 ` Cédric Le Goater
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