Re: [PATCH 2/7] target/riscv: Move target-agnostic definitions to 'cpu-qom.h'

[Paolo Bonzini <pbonzini@redhat.com>]

On 2/6/25 19:18, Philippe Mathieu-Daudé wrote:
> "cpu.h" is target-specific. Definitions which can be used
> by hw/ code when building QOM blocks can be in "cpu-qom.h",
> which is target-agnostic.
> 
> Move the MISA bits (removing the pointless target_ulong cast)
> and the IRQ index definitions.

This seems wrong.  Why not move from cpu.h to cpu_bits.h, and include that?

Paolo

> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/cpu-qom.h  | 40 ++++++++++++++++++++++++++++++++++++++++
>   target/riscv/cpu.h      | 24 ------------------------
>   target/riscv/cpu_bits.h | 15 ---------------
>   3 files changed, 40 insertions(+), 39 deletions(-)
> 
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index d56b067bf24..6028aa38fb2 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -55,4 +55,44 @@
>   
>   OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
>   
> +/* Interrupt causes */
> +#define IRQ_U_SOFT                         0
> +#define IRQ_S_SOFT                         1
> +#define IRQ_VS_SOFT                        2
> +#define IRQ_M_SOFT                         3
> +#define IRQ_U_TIMER                        4
> +#define IRQ_S_TIMER                        5
> +#define IRQ_VS_TIMER                       6
> +#define IRQ_M_TIMER                        7
> +#define IRQ_U_EXT                          8
> +#define IRQ_S_EXT                          9
> +#define IRQ_VS_EXT                         10
> +#define IRQ_M_EXT                          11
> +#define IRQ_S_GEXT                         12
> +#define IRQ_PMU_OVF                        13
> +
> +#define RV(x) (1UL << (x - 'A'))
> +
> +/*
> + * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
> + * when adding new MISA bits here.
> + */
> +#define RVI RV('I')
> +#define RVE RV('E') /* E and I are mutually exclusive */
> +#define RVM RV('M')
> +#define RVA RV('A')
> +#define RVF RV('F')
> +#define RVD RV('D')
> +#define RVV RV('V')
> +#define RVC RV('C')
> +#define RVS RV('S')
> +#define RVU RV('U')
> +#define RVH RV('H')
> +#define RVG RV('G')
> +#define RVB RV('B')
> +
> +extern const uint32_t misa_bits[];
> +const char *riscv_get_misa_ext_name(uint32_t bit);
> +const char *riscv_get_misa_ext_description(uint32_t bit);
> +
>   #endif /* RISCV_CPU_QOM_H */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 97713681cbe..4e681ad3917 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -54,30 +54,6 @@ typedef struct CPUArchState CPURISCVState;
>    */
>   #define RISCV_UW2_ALWAYS_STORE_AMO 1
>   
> -#define RV(x) ((target_ulong)1 << (x - 'A'))
> -
> -/*
> - * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
> - * when adding new MISA bits here.
> - */
> -#define RVI RV('I')
> -#define RVE RV('E') /* E and I are mutually exclusive */
> -#define RVM RV('M')
> -#define RVA RV('A')
> -#define RVF RV('F')
> -#define RVD RV('D')
> -#define RVV RV('V')
> -#define RVC RV('C')
> -#define RVS RV('S')
> -#define RVU RV('U')
> -#define RVH RV('H')
> -#define RVG RV('G')
> -#define RVB RV('B')
> -
> -extern const uint32_t misa_bits[];
> -const char *riscv_get_misa_ext_name(uint32_t bit);
> -const char *riscv_get_misa_ext_description(uint32_t bit);
> -
>   #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)
>   
>   typedef struct riscv_cpu_profile {
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index f97c48a3943..80701bc77fe 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -720,21 +720,6 @@ typedef enum RISCVException {
>   #define RISCV_EXCP_INT_FLAG                0x80000000
>   #define RISCV_EXCP_INT_MASK                0x7fffffff
>   
> -/* Interrupt causes */
> -#define IRQ_U_SOFT                         0
> -#define IRQ_S_SOFT                         1
> -#define IRQ_VS_SOFT                        2
> -#define IRQ_M_SOFT                         3
> -#define IRQ_U_TIMER                        4
> -#define IRQ_S_TIMER                        5
> -#define IRQ_VS_TIMER                       6
> -#define IRQ_M_TIMER                        7
> -#define IRQ_U_EXT                          8
> -#define IRQ_S_EXT                          9
> -#define IRQ_VS_EXT                         10
> -#define IRQ_M_EXT                          11
> -#define IRQ_S_GEXT                         12
> -#define IRQ_PMU_OVF                        13
>   #define IRQ_LOCAL_MAX                      64
>   /* -1 is due to bit zero of hgeip and hgeie being ROZ. */
>   #define IRQ_LOCAL_GUEST_MAX                (TARGET_LONG_BITS - 1)