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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-70803fc8b67sm64007b3a.128.2024.06.27.12.10.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jun 2024 12:10:42 -0700 (PDT) Message-ID: <1fecfba7-6a42-405c-a32a-e82164539650@linaro.org> Date: Thu, 27 Jun 2024 12:10:40 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/7] plugins: save value during memory accesses To: Pierrick Bouvier , qemu-devel@nongnu.org Cc: Alexandre Iooss , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Mahmoud Mandour , Paolo Bonzini , Eduardo Habkost , =?UTF-8?Q?Alex_Benn=C3=A9e?= References: <20240626233757.375083-1-pierrick.bouvier@linaro.org> <20240626233757.375083-3-pierrick.bouvier@linaro.org> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240626233757.375083-3-pierrick.bouvier@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/26/24 16:37, Pierrick Bouvier wrote: > Different code paths handle memory accesses: > - tcg generated code > - load/store helpers > - atomic helpers > > This value is saved in cpu->plugin_state. > > Atomic operations are doing read/write at the same time, so we generate > two memory callbacks instead of one, to allow plugins to access distinct > values. > > Signed-off-by: Pierrick Bouvier > --- > accel/tcg/atomic_template.h | 66 ++++++++++++++++++++++++++++---- > include/qemu/plugin.h | 8 ++++ > plugins/core.c | 7 ++++ > tcg/tcg-op-ldst.c | 72 +++++++++++++++++++++++++++++++---- > accel/tcg/atomic_common.c.inc | 13 ++++++- > accel/tcg/ldst_common.c.inc | 38 +++++++++++------- > 6 files changed, 173 insertions(+), 31 deletions(-) > > diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h > index 1dc2151dafd..830e4f16069 100644 > --- a/accel/tcg/atomic_template.h > +++ b/accel/tcg/atomic_template.h > @@ -53,6 +53,14 @@ > # error unsupported data size > #endif > > +#if DATA_SIZE == 16 > +# define UPPER_MEMORY_VALUE(val) int128_gethi(val) > +# define LOWER_MEMORY_VALUE(val) int128_getlo(val) > +#else > +# define UPPER_MEMORY_VALUE(val) 0 > +# define LOWER_MEMORY_VALUE(val) val > +#endif > + > #if DATA_SIZE >= 4 > # define ABI_TYPE DATA_TYPE > #else > @@ -83,7 +91,12 @@ ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, abi_ptr addr, > ret = qatomic_cmpxchg__nocheck(haddr, cmpv, newv); > #endif > ATOMIC_MMU_CLEANUP; > - atomic_trace_rmw_post(env, addr, oi); > + atomic_trace_rmw_post(env, addr, > + UPPER_MEMORY_VALUE(ret), > + LOWER_MEMORY_VALUE(ret), > + UPPER_MEMORY_VALUE(newv), > + LOWER_MEMORY_VALUE(newv), > + oi); Just a nit, but tcg is consistent in using little-endian argument ordering for values passed by parts. I would prefer we continue with that. > @@ -142,9 +142,13 @@ struct qemu_plugin_tb { > /** > * struct CPUPluginState - per-CPU state for plugins > * @event_mask: plugin event bitmap. Modified only via async work. > + * @mem_value_upper_bits: 64 upper bits of latest accessed mem value. > + * @mem_value_lower_bits: 64 lower bits of latest accessed mem value. > */ > struct CPUPluginState { > DECLARE_BITMAP(event_mask, QEMU_PLUGIN_EV_MAX); > + uint64_t mem_value_upper_bits; > + uint64_t mem_value_lower_bits; > }; At some point we may well support 32 byte acceses, for better guest vector support. Do we have a plan for this beyond "add more fields here"? r~