From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
Bin Meng <bin.meng@windriver.com>, Cleber Rosa <crosa@redhat.com>
Subject: Re: [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test
Date: Wed, 28 Dec 2022 13:59:57 +0100 [thread overview]
Message-ID: <1ff3c774-edaf-74cf-df57-ebcc7d75363f@linaro.org> (raw)
In-Reply-To: <20221228124242.184784-2-dbarboza@ventanamicro.com>
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
> This test is used to do a quick sanity check to ensure that we're able
> to run the existing QEMU FW image.
>
> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
> RISCV32_BIOS_BIN firmware with minimal options.
>
> The riscv32 'spike' machine isn't bootable at this moment, requiring an
> Opensbi fix [1] and QEMU side changes [2]. We could just leave at that
> or add a 'skip' test to remind us about it. To work as a reminder that
> we have a riscv32 'spike' test that should be enabled as soon as Opensbi
> QEMU rom receives the fix, we're adding a 'skip' test:
>
> (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike:
> SKIP: requires OpenSBI fix to work
>
> [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/
> [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159
>
> Cc: Cleber Rosa <crosa@redhat.com>
> Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++
> 1 file changed, 77 insertions(+)
> create mode 100644 tests/avocado/riscv_opensbi.py
>
> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py
> new file mode 100644
> index 0000000000..64fcf3c774
> --- /dev/null
> +++ b/tests/avocado/riscv_opensbi.py
> @@ -0,0 +1,77 @@
> +# opensbi boot test for RISC-V machines
s/opensbi/OpenSBI/
> +#
> +# Copyright (c) 2022, Ventana Micro
> +#
> +# This work is licensed under the terms of the GNU GPL, version 2 or
> +# later. See the COPYING file in the top-level directory.
> +
> +from avocado_qemu import QemuSystemTest
> +from avocado import skip
> +from avocado_qemu import wait_for_console_pattern
> +
> +class RiscvOpensbi(QemuSystemTest):
> + """
> + :avocado: tags=accel:tcg
> + """
> + timeout = 5
Easier to review common code once:
def boot_opensbi(self):
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, 'Platform Name')
wait_for_console_pattern(self, 'Boot HART MEDELEG')
> +
> + def test_riscv64_virt(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:virt
> + """
self.boot_opensbi()
> + def test_riscv64_spike(self):
> + """
> + :avocado: tags=arch:riscv64
> + :avocado: tags=machine:spike
> + """
self.boot_opensbi()
[...]
> + @skip("requires OpenSBI fix to work")
> + def test_riscv32_spike(self):
> + """
> + :avocado: tags=arch:riscv32
> + :avocado: tags=machine:spike
> + """
self.boot_opensbi()
next prev parent reply other threads:[~2022-12-28 13:00 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-28 12:42 [PATCH v2 00/10] riscv: opensbi boot test and cleanups Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test Daniel Henrique Barboza
2022-12-28 12:59 ` Philippe Mathieu-Daudé [this message]
2022-12-28 13:03 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 02/10] hw/riscv/spike: use 'fdt' from MachineState Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 03/10] hw/riscv/sifive_u: " Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 04/10] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 05/10] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 06/10] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 07/10] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 08/10] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 09/10] hw/riscv/boot.c: consolidate all kernel init " Daniel Henrique Barboza
2022-12-28 12:56 ` Philippe Mathieu-Daudé
2022-12-28 13:01 ` Daniel Henrique Barboza
2022-12-28 12:42 ` [PATCH v2 10/10] hw/riscv/boot.c: make riscv_load_initrd() static Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1ff3c774-edaf-74cf-df57-ebcc7d75363f@linaro.org \
--to=philmd@linaro.org \
--cc=alistair.francis@wdc.com \
--cc=bin.meng@windriver.com \
--cc=crosa@redhat.com \
--cc=dbarboza@ventanamicro.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).