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Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 01/10] tests/avocado: add RISC-V opensbi boot test Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Cleber Rosa References: <20221228124242.184784-1-dbarboza@ventanamicro.com> <20221228124242.184784-2-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20221228124242.184784-2-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.147, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 28/12/22 13:42, Daniel Henrique Barboza wrote: > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > The riscv32 'spike' machine isn't bootable at this moment, requiring an > Opensbi fix [1] and QEMU side changes [2]. We could just leave at that > or add a 'skip' test to remind us about it. To work as a reminder that > we have a riscv32 'spike' test that should be enabled as soon as Opensbi > QEMU rom receives the fix, we're adding a 'skip' test: > > (11/18) tests/avocado/riscv_opensbi.py:RiscvOpensbi.test_riscv32_spike: > SKIP: requires OpenSBI fix to work > > [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/ > [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 > > Cc: Cleber Rosa > Cc: Philippe Mathieu-Daudé > Signed-off-by: Daniel Henrique Barboza > --- > tests/avocado/riscv_opensbi.py | 77 ++++++++++++++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > new file mode 100644 > index 0000000000..64fcf3c774 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,77 @@ > +# opensbi boot test for RISC-V machines s/opensbi/OpenSBI/ > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado import skip > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=accel:tcg > + """ > + timeout = 5 Easier to review common code once: def boot_opensbi(self): self.vm.set_console() self.vm.launch() wait_for_console_pattern(self, 'Platform Name') wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:virt > + """ self.boot_opensbi() > + def test_riscv64_spike(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:spike > + """ self.boot_opensbi() [...] > + @skip("requires OpenSBI fix to work") > + def test_riscv32_spike(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:spike > + """ self.boot_opensbi()