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From: Rusty Russell <rusty@rustcorp.com.au>
Subject: Re: [Qemu-devel] Re: [PATCH] Updated Sparc support 
In-reply-to: Your message of "Tue, 13 May 2003 14:31:22 +0200."
             <3EC0E59A.5070907@free.fr>
Date: Wed, 14 May 2003 10:13:50 +1000
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To: qemu-devel@nongnu.org

In message <3EC0E59A.5070907@free.fr> you write:
> I also plan to add direct block chaining. I will try to make it portable 
> by using the 'goto *' gcc extension, but I don't know yet if it will 
> work on every CPU. The direct block chaining will generate something like:
> 
>   'goto *addr'
> 
> at the end of some translated blocks to jump either to the CPU core or 
> directly to the next translated block. 'addr' will be a global 'void *' 
> variable. Since no code will be patched to change block chaining, it 
> will simplify the instruction cache invalidation issues and the 
> threading issues.

Hmm, I had a more ambitious idea, and that was to keep simple stats on
which block last followed each block: if it goes to the same block
more than N times in a row, coalesce/chain them.

As blocks get longer, you have more opportunities for register
lifetime analsis, which could eliminate redundant stores to registers
in particular.

I haven't got actual code, so I haven't mentioned it before...

Thoughts?
Rusty.
--
  Anyone who quotes me in their sig is an idiot. -- Rusty Russell.