From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1BrODv-0007Fo-I8 for qemu-devel@nongnu.org; Sun, 01 Aug 2004 17:50:31 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.33) id 1BrODt-0007Fc-Vm for qemu-devel@nongnu.org; Sun, 01 Aug 2004 17:50:31 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1BrODr-0007FZ-US for qemu-devel@nongnu.org; Sun, 01 Aug 2004 17:50:29 -0400 Received: from [62.241.160.193] (helo=pengo.systems.pipex.net) by monty-python.gnu.org with esmtp (Exim 4.34) id 1BrOAI-0006V5-JU for qemu-devel@nongnu.org; Sun, 01 Aug 2004 17:46:46 -0400 Received: from nowt.org (81-178-252-250.dsl.pipex.com [81.178.252.250]) by pengo.systems.pipex.net (Postfix) with ESMTP id 051894C00047 for ; Sun, 1 Aug 2004 22:46:44 +0100 (BST) Received: from wren.home (wren.home [192.168.1.7]) by nowt.org (Postfix) with ESMTP id 6187BAC92 for ; Sun, 1 Aug 2004 22:46:44 +0100 (BST) From: Paul Brook Date: Sun, 1 Aug 2004 22:46:43 +0100 MIME-Version: 1.0 Content-Disposition: inline Content-Type: Multipart/Mixed; boundary="Boundary-00=_DTWDBxJ5nmC+uI5" Message-Id: <200408012246.43919.paul@codesourcery.com> Subject: [Qemu-devel] [patch] Fix arm rrx addressing mode Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --Boundary-00=_DTWDBxJ5nmC+uI5 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline The attached patch fixes the arm Rotate Right with Extend addressing mode. Paul --Boundary-00=_DTWDBxJ5nmC+uI5 Content-Type: text/x-diff; charset="us-ascii"; name="patch.qemu_rrx" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="patch.qemu_rrx" Index: target-arm/op.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-arm/op.c,v retrieving revision 1.3 diff -u -p -r1.3 op.c --- target-arm/op.c 30 Nov 2003 19:40:08 -0000 1.3 +++ target-arm/op.c 1 Aug 2004 21:43:22 -0000 @@ -485,6 +502,11 @@ void OPPROTO op_rorl_T1_im(void) T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift)); } +void OPPROTO op_rrxl_T1(void) +{ + T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); +} + /* T1 based, set C flag */ void OPPROTO op_shll_T1_im_cc(void) { @@ -512,6 +534,14 @@ void OPPROTO op_rorl_T1_im_cc(void) T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift)); } +void OPPROTO op_rrxl_T1_cc(void) +{ + uint32_t c; + c = T1 & 1; + T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); + env->CF = c; +} + /* T2 based */ void OPPROTO op_shll_T2_im(void) { Index: target-arm/translate.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-arm/translate.c,v retrieving revision 1.10 diff -u -p -r1.10 translate.c --- target-arm/translate.c 22 Jun 2004 10:55:49 -0000 1.10 +++ target-arm/translate.c 1 Aug 2004 21:43:22 -0000 @@ -365,6 +484,11 @@ static void disas_arm_insn(DisasContext } else { gen_shift_T1_im[shiftop](shift); } + } else if (shiftop == 3) { + if (logic_cc) + gen_op_rrxl_T1_cc(); + else + gen_op_rrxl_T1(); } } else { rs = (insn >> 8) & 0xf; --Boundary-00=_DTWDBxJ5nmC+uI5--