From: "Rafael Ávila de Espíndola" <rafael.espindola@ic.unicamp.br>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [patch] mnemonic asm names and clobber list
Date: Sat, 4 Sep 2004 14:09:35 -0300 [thread overview]
Message-ID: <200409041409.50470.rafael.espindola@ic.unicamp.br> (raw)
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The attached patch changes the "%n" in the inline asm used with CODE_COPY to
the more readable format %[mnemonic]. The patch also adds some missing
registers to the clobber list.
Rafael
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Index: cpu-exec.c
===================================================================
RCS file: /cvsroot/qemu/qemu/cpu-exec.c,v
retrieving revision 1.38
diff -u -r1.38 cpu-exec.c
--- cpu-exec.c 14 Jul 2004 17:20:55 -0000 1.38
+++ cpu-exec.c 4 Sep 2004 15:59:52 -0000
@@ -471,60 +471,61 @@
asm(".globl exec_loop\n"
"\n"
"debug1:\n"
+ " movl %[FUNC], %%eax\n"
" pushl %%ebp\n"
- " fs movl %10, %9\n"
- " fs movl %11, %%eax\n"
+ " fs movl %%eax, %[TMP0]\n"
+ " fs movl %[DFR], %%eax\n"
" andl $0x400, %%eax\n"
- " fs orl %8, %%eax\n"
+ " fs orl %[CCSRC], %%eax\n"
" pushl %%eax\n"
" popf\n"
- " fs movl %%esp, %12\n"
- " fs movl %0, %%eax\n"
- " fs movl %1, %%ecx\n"
- " fs movl %2, %%edx\n"
- " fs movl %3, %%ebx\n"
- " fs movl %4, %%esp\n"
- " fs movl %5, %%ebp\n"
- " fs movl %6, %%esi\n"
- " fs movl %7, %%edi\n"
- " fs jmp *%9\n"
+ " fs movl %%esp, %[SESP]\n"
+ " fs movl %[EAX], %%eax\n"
+ " fs movl %[ECX], %%ecx\n"
+ " fs movl %[EDX], %%edx\n"
+ " fs movl %[EBX], %%ebx\n"
+ " fs movl %[ESP], %%esp\n"
+ " fs movl %[EBP], %%ebp\n"
+ " fs movl %[ESI], %%esi\n"
+ " fs movl %[EDI], %%edi\n"
+ " fs jmp *%[TMP0]\n"
"exec_loop:\n"
- " fs movl %%esp, %4\n"
- " fs movl %12, %%esp\n"
- " fs movl %%eax, %0\n"
- " fs movl %%ecx, %1\n"
- " fs movl %%edx, %2\n"
- " fs movl %%ebx, %3\n"
- " fs movl %%ebp, %5\n"
- " fs movl %%esi, %6\n"
- " fs movl %%edi, %7\n"
+ " fs movl %%esp, %[ESP]\n"
+ " fs movl %[SESP], %%esp\n"
+ " fs movl %%eax, %[EAX]\n"
+ " fs movl %%ecx, %[ECX]\n"
+ " fs movl %%edx, %[EDX]\n"
+ " fs movl %%ebx, %[EBX]\n"
+ " fs movl %%ebp, %[EBP]\n"
+ " fs movl %%esi, %[ESI]\n"
+ " fs movl %%edi, %[EDI]\n"
" pushf\n"
" popl %%eax\n"
" movl %%eax, %%ecx\n"
" andl $0x400, %%ecx\n"
" shrl $9, %%ecx\n"
" andl $0x8d5, %%eax\n"
- " fs movl %%eax, %8\n"
+ " fs movl %%eax, %[CCSRC]\n"
" movl $1, %%eax\n"
" subl %%ecx, %%eax\n"
- " fs movl %%eax, %11\n"
- " fs movl %9, %%ebx\n" /* get T0 value */
+ " fs movl %%eax, %[DFR]\n"
+ " fs movl %[TMP0], %[T0]\n" /* T0 must match the value present in env->tmp0*/
" popl %%ebp\n"
- :
- : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
- "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
- "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
- "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
- "a" (gen_func),
- "m" (*(uint8_t *)offsetof(CPUState, df)),
- "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
- : "%ecx", "%edx"
+ : [T0] "=b" (T0)
+ : [EAX] "m" (*(uint8_t *)offsetof(CPUState, regs[R_EAX])),
+ [ECX] "m" (*(uint8_t *)offsetof(CPUState, regs[R_ECX])),
+ [EDX] "m" (*(uint8_t *)offsetof(CPUState, regs[R_EDX])),
+ [EBX] "m" (*(uint8_t *)offsetof(CPUState, regs[R_EBX])),
+ [ESP] "m" (*(uint8_t *)offsetof(CPUState, regs[R_ESP])),
+ [EBP] "m" (*(uint8_t *)offsetof(CPUState, regs[R_EBP])),
+ [ESI] "m" (*(uint8_t *)offsetof(CPUState, regs[R_ESI])),
+ [EDI] "m" (*(uint8_t *)offsetof(CPUState, regs[R_EDI])),
+ [CCSRC] "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
+ [TMP0] "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
+ [DFR] "m" (*(uint8_t *)offsetof(CPUState, df)),
+ [SESP] "m" (*(uint8_t *)offsetof(CPUState, saved_esp)),
+ [FUNC] "m" (gen_func)
+ : "%eax", "%ecx", "%edx", "%ebp", "%edi", "%esi", "memory"
);
}
}
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