From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.33) id 1CCeMf-0007hG-3p for qemu-devel@nongnu.org; Wed, 29 Sep 2004 09:19:25 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.33) id 1CCeMe-0007h1-L8 for qemu-devel@nongnu.org; Wed, 29 Sep 2004 09:19:24 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.33) id 1CCeMe-0007gq-F2 for qemu-devel@nongnu.org; Wed, 29 Sep 2004 09:19:24 -0400 Received: from [62.241.160.193] (helo=pengo.systems.pipex.net) by monty-python.gnu.org with esmtp (Exim 4.34) id 1CCeFp-0004cA-Pk for qemu-devel@nongnu.org; Wed, 29 Sep 2004 09:12:21 -0400 Received: from nowt.org (81-178-235-178.dsl.pipex.com [81.178.235.178]) by pengo.systems.pipex.net (Postfix) with ESMTP id 914E04C0034F for ; Wed, 29 Sep 2004 14:12:18 +0100 (BST) Received: from wren.home (wren.home [192.168.1.7]) by nowt.org (Postfix) with ESMTP id EC642AC95 for ; Wed, 29 Sep 2004 14:12:11 +0100 (BST) From: Paul Brook Subject: Re: [Qemu-devel] ix64 target support Date: Wed, 29 Sep 2004 14:12:11 +0100 References: <1096390325.4234.365.camel@fred.soliddesign.net> <1096407437.4234.711.camel@fred.soliddesign.net> In-Reply-To: <1096407437.4234.711.camel@fred.soliddesign.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200409291412.11100.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tuesday 28 September 2004 22:37, Joe Batt wrote: > Actually, I'm just interested in 64bit address space, so any 64 bit chip > with a Linux distro would be great. Would some old 64 bit risc chip > (Alhpa or HPPA) be easier? > > I assume a lot of the interrupt and memory management can be adapted > from the x86 qemu code. The SH2 was pretty simple in this respect and > there was only one "mode". Anyone out there want to help me work though > some of this? > > Volume 3 from > http://www.amd.com/us-en/Processors/DevelopWithAMD/0,,30_2252_739_7044,00.h >tml lists all the opcodes and what they do. I started the SH2 emulator by > writing tests for each opcode, then the implementation from a document like > this. Is there anything else I need to evaluate before I start > implementing opcodes? You'll probably also need to implement SSE+SSE2. Certainly the linux amd64 ABI uses these. Paul