Index: target-arm/op.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-arm/op.c,v
retrieving revision 1.3
diff -u -p -r1.3 op.c
--- target-arm/op.c	30 Nov 2003 19:40:08 -0000	1.3
+++ target-arm/op.c	1 Aug 2004 21:43:22 -0000
@@ -485,6 +502,11 @@ void OPPROTO op_rorl_T1_im(void)
     T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
 }
 
+void OPPROTO op_rrxl_T1(void)
+{
+    T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
+}
+
 /* T1 based, set C flag */
 void OPPROTO op_shll_T1_im_cc(void)
 {
@@ -512,6 +534,14 @@ void OPPROTO op_rorl_T1_im_cc(void)
     T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
 }
 
+void OPPROTO op_rrxl_T1_cc(void)
+{
+    uint32_t c;
+    c = T1 & 1;
+    T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
+    env->CF = c;
+}
+
 /* T2 based */
 void OPPROTO op_shll_T2_im(void)
 {
Index: target-arm/translate.c
===================================================================
RCS file: /cvsroot/qemu/qemu/target-arm/translate.c,v
retrieving revision 1.10
diff -u -p -r1.10 translate.c
--- target-arm/translate.c	22 Jun 2004 10:55:49 -0000	1.10
+++ target-arm/translate.c	1 Aug 2004 21:43:22 -0000
@@ -365,6 +484,11 @@ static void disas_arm_insn(DisasContext 
                     } else {
                         gen_shift_T1_im[shiftop](shift);
                     }
+                } else if (shiftop == 3) {
+                    if (logic_cc)
+                        gen_op_rrxl_T1_cc();
+                    else
+                        gen_op_rrxl_T1();
                 }
             } else {
                 rs = (insn >> 8) & 0xf;