From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org, Karl Magdsick <kmagnum@gmail.com>
Subject: Re: [Qemu-devel] x86_64 target
Date: Tue, 4 Jan 2005 14:29:50 +0000 [thread overview]
Message-ID: <200501041429.51792.paul@codesourcery.com> (raw)
In-Reply-To: <cd8ecdef05010318155f5e9820@mail.gmail.com>
On Tuesday 04 January 2005 02:15, Karl Magdsick wrote:
> The EMT Xeons implement all of the amd64 instructions that were in an
> early release of the instruction set reference, so I think a single
> 64-bit Linux kernel can boot and run on both amd64 and EMT Xeon chips.
> The EMT Xeons may implement all of the instructions announced before
> the name switch to amd64, but I'm not sure exactly when the name
> change occured and when the newer instructions were announced.
The Intel chips actually implement all the instructions except 3DNOW and add
SSE3, same as p4 vs. AthlonXP. These are the only instruction set
differences, and the only differences that are visible from userspace.
The other differences in the implementations are that the current generation
of Intel chips don't implement the NX bit, or have an IOMMU. I think there
are also differences in how pagetables are setup/managed though I'm not sure
about the details.
Paul
next prev parent reply other threads:[~2005-01-04 14:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-01-04 0:18 [Qemu-devel] x86_64 target Fabrice Bellard
2005-01-04 2:15 ` Karl Magdsick
2005-01-04 14:29 ` Paul Brook [this message]
2005-01-05 17:48 ` Jeebs
2005-01-04 6:31 ` [Qemu-devel] " Alexander E. Patrakov
2005-01-04 19:56 ` Fabrice Bellard
2005-01-06 12:10 ` [Qemu-devel] " Lennert Buytenhek
2005-01-06 12:42 ` Lennert Buytenhek
2005-01-17 17:54 ` [Qemu-devel] " Ronald
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