From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1D6UEa-0000Yq-A0 for qemu-devel@nongnu.org; Wed, 02 Mar 2005 08:49:58 -0500 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1D6UER-0000UA-TI for qemu-devel@nongnu.org; Wed, 02 Mar 2005 08:49:44 -0500 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1D6UEP-0000NI-04 for qemu-devel@nongnu.org; Wed, 02 Mar 2005 08:49:41 -0500 Received: from [195.135.220.2] (helo=Cantor.suse.de) by monty-python.gnu.org with esmtp (TLSv1:DES-CBC3-SHA:168) (Exim 4.34) id 1D6Tsj-0000Ge-Fs for qemu-devel@nongnu.org; Wed, 02 Mar 2005 08:27:17 -0500 Received: from hermes.suse.de (hermes-ext.suse.de [195.135.221.8]) (using TLSv1 with cipher EDH-RSA-DES-CBC3-SHA (168/168 bits)) (No client certificate requested) by Cantor.suse.de (Postfix) with ESMTP id C10291545587 for ; Wed, 2 Mar 2005 14:27:15 +0100 (CET) From: Ulrich Hecht Subject: Re: [Qemu-devel] *-user fixes Date: Wed, 2 Mar 2005 14:27:12 +0100 References: <200502231250.22518.uli@suse.de> In-Reply-To: <200502231250.22518.uli@suse.de> MIME-Version: 1.0 Content-Type: Multipart/Mixed; boundary="Boundary-00=_x8bJCqCqtRje8I2" Message-Id: <200503021427.13142.uli@suse.de> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org --Boundary-00=_x8bJCqCqtRje8I2 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Hi! On Wednesday 23 February 2005 12:50, Ulrich Hecht wrote: > qemu-sigfpe.patch: > send SIGFPE in case of ARM FPA exceptions. No idea if this is 100% > correct, but it's good enough to convince the glibc test suite. Not the python test suite, though. Here's a better fix that, as an added bonus, may actually be correct. > qemu-syscalls.patch: > some trivial syscall implementations; I only needed (and tested) > madvise, but while I was there I noticed a number of other syscalls > that can be implemented without much effort. > > qemu-jobsignals.patch: > proper SIGTSTP/SIGCONT default handling; makes suspending/resuming my > editor work. So what about those, Fabrice? CU Uli --Boundary-00=_x8bJCqCqtRje8I2 Content-Type: text/x-diff; charset="utf-8"; name="qemu-arm-sigfpe.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="qemu-arm-sigfpe.patch" Index: linux-user/main.c =================================================================== RCS file: /cvsroot/qemu/qemu/linux-user/main.c,v retrieving revision 1.61 diff -u -r1.61 main.c --- linux-user/main.c 19 Feb 2005 17:25:31 -0000 1.61 +++ linux-user/main.c 2 Mar 2005 12:37:49 -0000 @@ -325,18 +325,45 @@ { TaskState *ts = env->opaque; uint32_t opcode; + int rc; /* we handle the FPU emulation here, as Linux */ /* we get the opcode */ opcode = ldl_raw((uint8_t *)env->regs[15]); - if (EmulateAll(opcode, &ts->fpa, env->regs) == 0) { + if ((rc=EmulateAll(opcode, &ts->fpa, env->regs)) == 0) { /* illegal instruction */ info.si_signo = SIGILL; info.si_errno = 0; info.si_code = TARGET_ILL_ILLOPN; info._sifields._sigfault._addr = env->regs[15]; queue_signal(info.si_signo, &info); - } else { + } else if (rc < 0) { /* FP exception */ + FPSR fpsr = ts->fpa.fpsr; + //printf("fpsr 0x%x, -rc 0x%x\n",fpsr,-rc); + if(fpsr & (-rc << 16)) /* exception enabled? */ + { + info.si_signo = SIGFPE; + info.si_errno = 0; + /* ordered by priority, least first */ + if(-rc & BIT_IXC) info.si_code = TARGET_FPE_FLTRES; + if(-rc & BIT_UFC) info.si_code = TARGET_FPE_FLTUND; + if(-rc & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF; + if(-rc & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV; + if(-rc & BIT_IOC) info.si_code = TARGET_FPE_FLTINV; + info._sifields._sigfault._addr = env->regs[15]; + queue_signal(info.si_signo, &info); + } + else + env->regs[15] += 4; + + /* accumulate unenabled exceptions */ + if((!(fpsr & BIT_IXE)) && (-rc & BIT_IXC)) fpsr |= BIT_IXC; + if((!(fpsr & BIT_UFE)) && (-rc & BIT_UFC)) fpsr |= BIT_UFC; + if((!(fpsr & BIT_OFE)) && (-rc & BIT_OFC)) fpsr |= BIT_OFC; + if((!(fpsr & BIT_DZE)) && (-rc & BIT_DZC)) fpsr |= BIT_DZC; + if((!(fpsr & BIT_IOE)) && (-rc & BIT_IOC)) fpsr |= BIT_IOC; + ts->fpa.fpsr=fpsr; + } else { /* everything OK */ /* increment PC */ env->regs[15] += 4; } Index: target-arm/nwfpe/fpa11.c =================================================================== RCS file: /cvsroot/qemu/qemu/target-arm/nwfpe/fpa11.c,v retrieving revision 1.1 diff -u -r1.1 fpa11.c --- target-arm/nwfpe/fpa11.c 16 Feb 2004 21:43:58 -0000 1.1 +++ target-arm/nwfpe/fpa11.c 2 Mar 2005 12:37:50 -0000 @@ -155,6 +155,8 @@ SetRoundingPrecision(ROUND_EXTENDED); fpa11->initflag = 1; } + + float_exception_flags = 0; if (TEST_OPCODE(opcode,MASK_CPRT)) { @@ -185,6 +187,11 @@ } // restore_flags(flags); + if(nRc == 1 && float_exception_flags) + { + //printf("fef 0x%x\n",float_exception_flags); + nRc=-float_exception_flags; + } //printf("returning %d\n",nRc); return(nRc); --Boundary-00=_x8bJCqCqtRje8I2--