From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DLoWg-0005rN-VY for qemu-devel@nongnu.org; Wed, 13 Apr 2005 16:31:55 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1DLoWN-0005mP-4d for qemu-devel@nongnu.org; Wed, 13 Apr 2005 16:31:36 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DLoWJ-0005hY-SV for qemu-devel@nongnu.org; Wed, 13 Apr 2005 16:31:31 -0400 Received: from [212.227.126.177] (helo=moutng.kundenserver.de) by monty-python.gnu.org with esmtp (Exim 4.34) id 1DLomQ-0000ls-1Z for qemu-devel@nongnu.org; Wed, 13 Apr 2005 16:48:10 -0400 From: Volker Ruppert Date: Wed, 13 Apr 2005 22:48:53 +0200 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200504132248.53304.info@vruppert.de> Subject: [Qemu-devel] [PATCH] Cirrus bugfixes Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hi all, here are some fixes for the Cirrus emulation. The patch fixes problems with the ISA version when running Win 3.11 and some display errors in Win95/98 and maybe others. - partial implementation of the destination write mask (bit 7 unhandled) - fixed banked memory access of the ISA version - the bus type bits in sequencer reg 0x17 must be readonly - fixed destination write mask in debug message diff -urN /home/volker/qemu/hw/cirrus_vga.c ./hw/cirrus_vga.c --- /home/volker/qemu/hw/cirrus_vga.c 2005-01-26 21:35:30.000000000 +0100 +++ ./hw/cirrus_vga.c 2005-04-10 15:28:17.000000000 +0200 @@ -800,7 +800,7 @@ s->cirrus_blt_srcpitch, s->cirrus_blt_dstaddr, s->cirrus_blt_srcaddr, - s->sr[0x2f]); + s->gr[0x2f]); #endif switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) { @@ -1042,10 +1042,10 @@ else offset <<= 12; - if (s->vram_size <= offset) + if (s->real_vram_size <= offset) limit = 0; else - limit = s->vram_size - offset; + limit = s->real_vram_size - offset; if (((s->gr[0x0b] & 0x01) == 0) && (bank_index != 0)) { if (limit > 0x8000) { @@ -1213,7 +1213,7 @@ #endif break; case 0x17: // Configuration Readback and Extended Control - s->sr[reg_index] = reg_value; + s->sr[reg_index] = (s->sr[reg_index] & 0x38) | (reg_value & 0xc7); cirrus_update_memory_access(s); break; default: diff -urNX /home/volker/exclude-qemu /home/volker/qemu/hw/cirrus_vga_rop2.h ./hw/cirrus_vga_rop2.h --- /home/volker/qemu/hw/cirrus_vga_rop2.h 2004-07-06 17:35:16.000000000 +0200 +++ ./hw/cirrus_vga_rop2.h 2005-04-12 17:48:31.106020808 +0200 @@ -47,6 +47,7 @@ int x, y, pattern_y, pattern_pitch, pattern_x; unsigned int col; const uint8_t *src1; + int skipleft = (s->gr[0x2f] & 0x07) * (DEPTH / 8); #if DEPTH == 8 pattern_pitch = 8; @@ -56,11 +57,11 @@ pattern_pitch = 32; #endif pattern_y = s->cirrus_blt_srcaddr & 7; - pattern_x = 0; + pattern_x = skipleft; for(y = 0; y < bltheight; y++) { - d = dst; + d = dst + skipleft; src1 = src + pattern_y * pattern_pitch; - for (x = 0; x < bltwidth; x += (DEPTH / 8)) { + for (x = skipleft; x < bltwidth; x += (DEPTH / 8)) { #if DEPTH == 8 col = src1[pattern_x]; pattern_x = (pattern_x + 1) & 7; @@ -99,7 +100,8 @@ unsigned int col; unsigned bitmask; unsigned index; - int srcskipleft = 0; + int srcskipleft = s->gr[0x2f] & 0x07; + int dstskipleft = srcskipleft * (DEPTH / 8); if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) { bits_xor = 0xff; @@ -112,8 +114,8 @@ for(y = 0; y < bltheight; y++) { bitmask = 0x80 >> srcskipleft; bits = *src++ ^ bits_xor; - d = dst; - for (x = 0; x < bltwidth; x += (DEPTH / 8)) { + d = dst + dstskipleft; + for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) { if ((bitmask & 0xff) == 0) { bitmask = 0x80; bits = *src++ ^ bits_xor; @@ -142,15 +144,16 @@ unsigned bits; unsigned int col; unsigned bitmask; - int srcskipleft = 0; + int srcskipleft = s->gr[0x2f] & 0x07; + int dstskipleft = srcskipleft * (DEPTH / 8); colors[0] = s->cirrus_blt_bgcol; colors[1] = s->cirrus_blt_fgcol; for(y = 0; y < bltheight; y++) { bitmask = 0x80 >> srcskipleft; bits = *src++; - d = dst; - for (x = 0; x < bltwidth; x += (DEPTH / 8)) { + d = dst + dstskipleft; + for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) { if ((bitmask & 0xff) == 0) { bitmask = 0x80; bits = *src++; @@ -175,6 +178,8 @@ int x, y, bitpos, pattern_y; unsigned int bits, bits_xor; unsigned int col; + int srcskipleft = s->gr[0x2f] & 0x07; + int dstskipleft = srcskipleft * (DEPTH / 8); if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) { bits_xor = 0xff; @@ -187,9 +192,9 @@ for(y = 0; y < bltheight; y++) { bits = src[pattern_y] ^ bits_xor; - bitpos = 7; - d = dst; - for (x = 0; x < bltwidth; x += (DEPTH / 8)) { + bitpos = 7 - srcskipleft; + d = dst + dstskipleft; + for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) { if ((bits >> bitpos) & 1) { PUTPIXEL(); } @@ -213,6 +218,8 @@ int x, y, bitpos, pattern_y; unsigned int bits; unsigned int col; + int srcskipleft = s->gr[0x2f] & 0x07; + int dstskipleft = srcskipleft * (DEPTH / 8); colors[0] = s->cirrus_blt_bgcol; colors[1] = s->cirrus_blt_fgcol; @@ -220,9 +227,9 @@ for(y = 0; y < bltheight; y++) { bits = src[pattern_y]; - bitpos = 7; - d = dst; - for (x = 0; x < bltwidth; x += (DEPTH / 8)) { + bitpos = 7 - srcskipleft; + d = dst + dstskipleft; + for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) { col = colors[(bits >> bitpos) & 1]; PUTPIXEL(); d += (DEPTH / 8);