From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1DYAg2-0000FY-Qz for qemu-devel@nongnu.org; Tue, 17 May 2005 18:36:39 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1DYAg1-0000Ez-M6 for qemu-devel@nongnu.org; Tue, 17 May 2005 18:36:37 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1DYAbg-00072E-Oj for qemu-devel@nongnu.org; Tue, 17 May 2005 18:32:08 -0400 Received: from [65.74.133.9] (helo=mail.codesourcery.com) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1DY8na-00056a-5X for qemu-devel@nongnu.org; Tue, 17 May 2005 16:36:18 -0400 From: Paul Brook Subject: Re: [Qemu-devel] Re: request : qemu-smp as target Date: Tue, 17 May 2005 21:21:28 +0100 References: <4285EC1E.4090904@bellard.org> <1116089712.18405.14.camel@fred.ofc.soliddesign.net> In-Reply-To: <1116089712.18405.14.camel@fred.ofc.soliddesign.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200505172121.28546.paul@codesourcery.com> Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Joe Batt > What inter processor synchronization issues are there? Could you take > this a step further and use processes on different machines for each > processor? (There are many shared memory implementations to choose > from.) Are there so many resources shared > between the CPUs to make this a ridiculous proposition? Baically most SMP/shared memory systems assume very low latency communication between CPUs and memory. For example on opteron systems remote memory latency is of the order of 200 cpu cycles. Typical ethernet latency is several million cycles. To do single-system image over a high latency interconnect (eg. ethernet) you need OS and preferably use application support to avoid high-contention memory areas. Simulating a SMP system over multiple separate nodes is theoretically possible, but performance would probaby be abysmal. The only solution I can imagine being even vaguely worthwhile is a running user-mode qemu on top of a native openmozix system. > I have ignorantly implemented an SH2 emulator, Cool. Any chance you're going to make these changes publicly available? Paul