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From: Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] [patch] gcc4 host support
Date: Wed, 18 May 2005 17:02:18 +0100
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To: qemu-devel@nongnu.org
Cc: David Woodhouse <dwmw2@infradead.org>

On Wednesday 18 May 2005 11:06, Herbert Poetzl wrote:
> On Tue, May 17, 2005 at 09:46:30PM +0100, Paul Brook wrote:
> > On Monday 16 May 2005 10:41, David Woodhouse wrote:
> > > On Wed, 2005-05-11 at 22:04 +0100, Paul Brook wrote:
> > > > My solution is to search the function for the "ret" instruction and
> > > > replace them with a jmp to the next block of code. On RISC targets
> > > > this would be easy.
> > >
> > > About this easy, in fact...
> > >...
> > > +
> > > +		if (get32((uint32_t *)p) == 0x4e800020) {
> > > +		    blr_addr = p;
> > > +		    copy_size = p_end - p_start;
> > > +		    break;
> > > +		}
> >
> > You probably want to scan the whole function to check there aren't
> > multiple blr instructions, and throw an error if there are.
>
> hmm, wouldn't it be much easier to separate compiling
> from assembling, and do the 'changes' on the assembler
> files instead?

For x86 maybe. For ppc it's easier to just scan the binary code.
You'd have to write an assembly code parser.

Paul