qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [Qemu-devel] Qemu for MIPS
@ 2005-06-13 10:59 Ralf Baechle
  2005-06-13 11:44 ` [Qemu-devel] " Dominic Sweetman
  2005-06-13 11:50 ` [Qemu-devel] " Timo Savola
  0 siblings, 2 replies; 8+ messages in thread
From: Ralf Baechle @ 2005-06-13 10:59 UTC (permalink / raw)
  To: qemu-devel, linux-mips; +Cc: Jocelyn Mayer

I've posted updated Qemu patches on

  ftp://ftp.linux-mips.org/pub/linux/mips/qemu
  http://www.linux-mips.org/wiki/index.php/Qemu

Enhancements over last week's patches:

 o The count/compare interrupt will now properly be delivered.
 o mfc0 will now return the proper value for the EXL and ERL flags
 o eret will now consider the value of ERL and EXL.
 o i8259 PIC is now properly cascaded to a CPU interrupt.
 o An ISA NE2000 card will now be emulated.
 o The CPU's random register now considers the value of the wired register

The new kernel patch is against the latest Linux/MIPS CVS kernel du jour
2.6.12-rc6 and has been updated to match Qemu's improvments.

Known bugs:

 o ll/sc don't use a ll_bit like the real hardware thus right now any atomic
   functions aren't really atomic.
 o ll/sc really should be watching a physical not a virtual address or they
   won't do much useful on any kind of shared memory structure.
 o MIPS documentation documents the lladdr register to contain the virtual
   address of the location being watched but about every implementation
   since the R4000 actually keeps the physical address there - and documents
   that as an erratum even though it actually the sensible thing to do.  We
   should do the same.  Fortunately nothing that I know of actually relies
   on the content of the lladdr register, so this one is cosmetic.

Last, not least, this is what you've been waiting for:

[root@dea qemu-mips]# mips-softmmu/qemu-system-mips -kernel ~ralf/src/linux/linux-cvs/arch/mips/boot/vmlinux.bin -m 16 -nographic
nb_nics = 1
Connected to host network interface: tun0
/etc/qemu-ifup tun0
+ ifconfig tun0 up
+ brctl addbr qnet
device qnet already exists; can't create bridge with the same name
+ brctl addif qnet tun0
+ ifconfig qnet 172.20.0.1
(qemu) mips_r4k_init: start
mips_r4k_init: load BIOS '/usr/local/share/qemu/mips_bios.bin' size 131072
Linux version 2.6.12-rc5 (ralf@dea.linux-mips.net) (gcc version 3.4.3) #257 Mon Jun 13 02:58:23 BST 2005
CPU revision is: 00018000
Determined physical RAM map:
 memory: 01000000 @ 00000000 (usable)
On node 0 totalpages: 4096
  DMA zone: 4096 pages, LIFO batch:1
  Normal zone: 0 pages, LIFO batch:1
  HighMem zone: 0 pages, LIFO batch:1
Built 1 zonelists
Kernel command line: console=ttyS0 debug ip=172.20.0.2:172.20.0.1::255.255.0.0
Primary instruction cache 2kB, physically tagged, 2-way, linesize 16 bytes.
Primary data cache 2kB, 2-way, linesize 16 bytes.
Synthesized TLB refill handler (19 instructions).
Synthesized TLB load handler fastpath (31 instructions).
Synthesized TLB store handler fastpath (31 instructions).
Synthesized TLB modify handler fastpath (30 instructions).
PID hash table entries: 128 (order: 7, 2048 bytes)
Using 100.000 MHz high precision timer.
Console: colour VGA+ 80x25
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Memory: 14464k/16384k available (1293k kernel code, 1900k reserved, 190k data, 104k init, 0k highmem)
Calibrating delay loop... 144.58 BogoMIPS (lpj=722944)
Mount-cache hash table entries: 512
Checking for 'wait' instruction...  available.
NET: Registered protocol family 16
Serial: 8250/16550 driver $Revision: 1.90 $ 8 ports, IRQ sharing disabled
ttyS0 at I/O 0x3f8 (irq = 4) is a 16450
io scheduler noop registered
ne.c:v1.10 9/23/94 Donald Becker (becker@scyld.com)
Last modified Nov 1, 2000 by Paul Gortmaker
NE*000 ethercard probe at 0x300: 52 54 00 12 34 56
eth0: NE2000 found at 0x300, using IRQ 9.
NET: Registered protocol family 2
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP established hash table entries: 1024 (order: 1, 8192 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
NET: Registered protocol family 1
NET: Registered protocol family 17
IP-Config: Complete:
      device=eth0, addr=172.20.0.2, mask=255.255.0.0, gw=255.255.255.255,
     host=172.20.0.2, domain=, nis-domain=(none),
     bootserver=172.20.0.1, rootserver=172.20.0.1, rootpath=
Looking up port of RPC 100003/2 on 172.20.0.1
Looking up port of RPC 100005/1 on 172.20.0.1
VFS: Mounted root (nfs filesystem) readonly.
Freeing unused kernel memory: 104k freed
Kernel panic - not syncing: No init found.  Try passing init= option to kernel.

Which is a bug - there is a valid root filesystem.  Something for tomorrow.

Enjoy,

  Ralf

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [Qemu-devel] Re: Qemu for MIPS
  2005-06-13 10:59 [Qemu-devel] Qemu for MIPS Ralf Baechle
@ 2005-06-13 11:44 ` Dominic Sweetman
  2005-06-13 12:56   ` Ralf Baechle
  2005-06-13 11:50 ` [Qemu-devel] " Timo Savola
  1 sibling, 1 reply; 8+ messages in thread
From: Dominic Sweetman @ 2005-06-13 11:44 UTC (permalink / raw)
  To: Ralf Baechle; +Cc: linux-mips, Jocelyn Mayer, qemu-devel


Ralf Baechle (ralf@linux-mips.org) writes:

> I've posted updated Qemu patches on
> 
>   ftp://ftp.linux-mips.org/pub/linux/mips/qemu
>   http://www.linux-mips.org/wiki/index.php/Qemu
> 
> Enhancements over last week's patches:
> 
>  o The count/compare interrupt will now properly be delivered.
>  o mfc0 will now return the proper value for the EXL and ERL flags
>  o eret will now consider the value of ERL and EXL.
>  o i8259 PIC is now properly cascaded to a CPU interrupt.
>  o An ISA NE2000 card will now be emulated.
>  o The CPU's random register now considers the value of the wired register

Great stuff...

> Known bugs:
> 
>  o ll/sc don't use a ll_bit like the real hardware thus right now any atomic
>    functions aren't really atomic.

I suppose you know that the CPUs all implement "break link on
exception" by zeroing the link bit on an 'eret'?  That doesn't sound
too hard...

>  o ll/sc really should be watching a physical not a virtual address or they
>    won't do much useful on any kind of shared memory structure.
>  o MIPS documentation documents the lladdr register to contain the virtual
>    address of the location being watched but about every implementation
>    since the R4000 actually keeps the physical address there - and documents
>    that as an erratum even though it actually the sensible thing to do.  We
>    should do the same.  Fortunately nothing that I know of actually relies
>    on the content of the lladdr register, so this one is cosmetic.

Arguably, an emulator should not provide the LLaddr register at all.
It's optional and "only available for debug" - and probably such
debugging is possible another way in an emulator.  Robust software
shouldn't depend on assuming the contents make sense.

> ...
> Kernel panic - not syncing: No init found.  Try passing init= option to kernel.
> 
> Which is a bug - there is a valid root filesystem.  Something for tomorrow.

Not quite there yet... but well done, again.

--
Dominic

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Qemu-devel] Qemu for MIPS
  2005-06-13 10:59 [Qemu-devel] Qemu for MIPS Ralf Baechle
  2005-06-13 11:44 ` [Qemu-devel] " Dominic Sweetman
@ 2005-06-13 11:50 ` Timo Savola
  2005-06-13 12:41   ` Ralf Baechle
  2005-06-13 13:01   ` Thomas Petazzoni
  1 sibling, 2 replies; 8+ messages in thread
From: Timo Savola @ 2005-06-13 11:50 UTC (permalink / raw)
  To: Jocelyn Mayer; +Cc: qemu-devel

Are there any plans for supporting user-mode MIPS emulation?

timo

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Qemu-devel] Qemu for MIPS
  2005-06-13 11:50 ` [Qemu-devel] " Timo Savola
@ 2005-06-13 12:41   ` Ralf Baechle
  2005-06-13 12:47     ` Hetz Ben Hamo
  2005-06-13 13:01   ` Thomas Petazzoni
  1 sibling, 1 reply; 8+ messages in thread
From: Ralf Baechle @ 2005-06-13 12:41 UTC (permalink / raw)
  To: qemu-devel, linux-mips; +Cc: Jocelyn Mayer

On Mon, Jun 13, 2005 at 02:50:37PM +0300, Timo Savola wrote:

> Are there any plans for supporting user-mode MIPS emulation?

At some point certainly but right now my priority is full system emulation.

  Ralf

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Qemu-devel] Qemu for MIPS
  2005-06-13 12:41   ` Ralf Baechle
@ 2005-06-13 12:47     ` Hetz Ben Hamo
  2005-06-13 13:41       ` Ralf Baechle
  0 siblings, 1 reply; 8+ messages in thread
From: Hetz Ben Hamo @ 2005-06-13 12:47 UTC (permalink / raw)
  To: qemu-devel

Full system to boot Irix?

Hetz

On 6/13/05, Ralf Baechle <ralf@linux-mips.org> wrote:
> On Mon, Jun 13, 2005 at 02:50:37PM +0300, Timo Savola wrote:
> 
> > Are there any plans for supporting user-mode MIPS emulation?
> 
> At some point certainly but right now my priority is full system emulation.
> 
>   Ralf
> 
> 
> _______________________________________________
> Qemu-devel mailing list
> Qemu-devel@nongnu.org
> http://lists.nongnu.org/mailman/listinfo/qemu-devel
>

^ permalink raw reply	[flat|nested] 8+ messages in thread

* [Qemu-devel] Re: Qemu for MIPS
  2005-06-13 11:44 ` [Qemu-devel] " Dominic Sweetman
@ 2005-06-13 12:56   ` Ralf Baechle
  0 siblings, 0 replies; 8+ messages in thread
From: Ralf Baechle @ 2005-06-13 12:56 UTC (permalink / raw)
  To: Dominic Sweetman; +Cc: linux-mips, Jocelyn Mayer, qemu-devel

On Mon, Jun 13, 2005 at 12:44:09PM +0100, Dominic Sweetman wrote:

> > Known bugs:
> > 
> >  o ll/sc don't use a ll_bit like the real hardware thus right now any atomic
> >    functions aren't really atomic.
> 
> I suppose you know that the CPUs all implement "break link on
> exception" by zeroing the link bit on an 'eret'?  That doesn't sound
> too hard...

It's not hard to add the llbit indeed - maybe I'm trying to hard to be
obscure use compatible.  Generally Qemu is trading the highest accuracy
of emulation for speed ...

> Arguably, an emulator should not provide the LLaddr register at all.
> It's optional and "only available for debug" - and probably such
> debugging is possible another way in an emulator.  Robust software
> shouldn't depend on assuming the contents make sense.

The only use I've seen for this register is having it being used as a
cp0 scratch register allowing to save the entire 31 GPRs.  Very old
Linux/MIPS used to do that but it doesn't match the reality of MIPS ABIs,
so I gave up on that very soon.  Like 11 years agp :)

> Not quite there yet... but well done, again.

  Ralf

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Qemu-devel] Qemu for MIPS
  2005-06-13 11:50 ` [Qemu-devel] " Timo Savola
  2005-06-13 12:41   ` Ralf Baechle
@ 2005-06-13 13:01   ` Thomas Petazzoni
  1 sibling, 0 replies; 8+ messages in thread
From: Thomas Petazzoni @ 2005-06-13 13:01 UTC (permalink / raw)
  To: qemu-devel

Hello,

Timo Savola wrote:

> Are there any plans for supporting user-mode MIPS emulation?

http://lists.gnu.org/archive/html/qemu-devel/2005-02/msg00081.html
http://lists.gnu.org/archive/html/qemu-devel/2005-06/msg00114.html

Sincerly,

Thomas
-- 
Thomas Petazzoni
thomas.petazzoni@enix.org

^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [Qemu-devel] Qemu for MIPS
  2005-06-13 12:47     ` Hetz Ben Hamo
@ 2005-06-13 13:41       ` Ralf Baechle
  0 siblings, 0 replies; 8+ messages in thread
From: Ralf Baechle @ 2005-06-13 13:41 UTC (permalink / raw)
  To: Hetz Ben Hamo, qemu-devel

On Mon, Jun 13, 2005 at 02:47:48PM +0200, Hetz Ben Hamo wrote:

> Full system to boot Irix?

That would require emulation of an IRIX-supported platform.  Not undoable -
others have already gotten firmware as complex as the SGI ARC [1]
firmware to run on other emulators, I think it was mips64emul.

Windows NT for MIPS would be another thing to try ;-)

  Ralf

[1] And remember it writes ARC but pronounces ARRRRGGGGHHHH...

^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2005-06-13 13:55 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2005-06-13 10:59 [Qemu-devel] Qemu for MIPS Ralf Baechle
2005-06-13 11:44 ` [Qemu-devel] " Dominic Sweetman
2005-06-13 12:56   ` Ralf Baechle
2005-06-13 11:50 ` [Qemu-devel] " Timo Savola
2005-06-13 12:41   ` Ralf Baechle
2005-06-13 12:47     ` Hetz Ben Hamo
2005-06-13 13:41       ` Ralf Baechle
2005-06-13 13:01   ` Thomas Petazzoni

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).