From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1E4arj-0000B0-Oj for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:02:43 -0400 Received: from exim by lists.gnu.org with spam-scanned (Exim 4.43) id 1E4arh-00009v-1v for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:02:42 -0400 Received: from [199.232.76.173] (helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1E4arg-00009F-Nb for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:02:41 -0400 Received: from [62.254.210.129] (helo=bacchus.net.dhis.org) by monty-python.gnu.org with esmtp (TLS-1.0:DHE_RSA_3DES_EDE_CBC_SHA:24) (Exim 4.34) id 1E4b36-0007CG-Ok for qemu-devel@nongnu.org; Mon, 15 Aug 2005 05:14:29 -0400 Date: Mon, 15 Aug 2005 09:58:42 +0100 From: Ralf Baechle Message-ID: <20050815085842.GA7650@linux-mips.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] [PATCH 3/3] Fix interrupt masking Reply-To: qemu-devel@nongnu.org List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabrice Bellard , qemu-devel@nongnu.org Only take interrupts that are actually enabled in the CPU's interrupt mask in c0_status. cpu-exec.c | 2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: qemu-mips/cpu-exec.c =================================================================== --- qemu-mips.orig/cpu-exec.c +++ qemu-mips/cpu-exec.c @@ -307,7 +307,7 @@ int cpu_exec(CPUState *env1) #elif defined(TARGET_MIPS) if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->CP0_Status & (1 << CP0St_IE)) && - (env->CP0_Cause & 0x0000FF00) && + (env->CP0_Status & env->CP0_Cause & 0x0000FF00) && !(env->hflags & MIPS_HFLAG_EXL) && !(env->hflags & MIPS_HFLAG_ERL) && !(env->hflags & MIPS_HFLAG_DM)) {